Searched hist:10502 (Results 1 - 3 of 3) sorted by relevance

/gem5/src/mem/cache/
H A Dmshr.hh10502:f2f1dbfd505e Thu Oct 30 00:18:00 EDT 2014 Curtis Dunham <Curtis.Dunham@arm.com> mem: have WriteInvalidate obsolete MSHRs

Since WriteInvalidate directly writes into the cache, it can
create tricky timing interleavings with reads and writes to the
same cache line that haven't yet completed. This patch ensures
that these requests, when completed, don't overwrite the newer
data from the WriteInvalidate.
H A Dmshr.cc10502:f2f1dbfd505e Thu Oct 30 00:18:00 EDT 2014 Curtis Dunham <Curtis.Dunham@arm.com> mem: have WriteInvalidate obsolete MSHRs

Since WriteInvalidate directly writes into the cache, it can
create tricky timing interleavings with reads and writes to the
same cache line that haven't yet completed. This patch ensures
that these requests, when completed, don't overwrite the newer
data from the WriteInvalidate.
/gem5/src/arch/arm/
H A Dutility.cc12712:246dfbaf28a2 Mon May 14 09:48:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: MPIDR.MT = 1 in a multithreaded system

MPIDR.MT Indicates whether the lowest level of affinity consists of
logical PEs that are implemented using a multithreading type approach

Change-Id: Ia5e6e65577729c7826227c4574ce690f76454edc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10502
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

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