Searched refs:spsr (Results 1 - 4 of 4) sorted by relevance

/gem5/src/arch/arm/insts/
H A Dstatic_inst.cc1021 getRestoredITBits(ThreadContext *tc, CPSR spsr)
1025 const ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t)spsr.mode);
1026 const uint8_t it = itState(spsr);
1028 if (!spsr.t || spsr.il)
1050 illegalExceptionReturn(ThreadContext *tc, CPSR cpsr, CPSR spsr)
1052 const OperatingMode mode = (OperatingMode) (uint8_t)spsr.mode;
1074 bool spsr_mode_is_aarch32 = (spsr.width == 1);
1082 if (!spsr.width) {
1086 if (spsr
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H A Dstatic_inst.hh281 spsrWriteByInstr(uint32_t spsr, uint32_t val, argument
295 return ((spsr & ~bitMask) | (val & bitMask));
496 CPSR getPSTATEFromPSR(ThreadContext *tc, CPSR cpsr, CPSR spsr) const;
/gem5/src/arch/arm/
H A Dfaults.cc645 CPSR spsr = cpsr; local
646 spsr.nz = tc->readCCReg(CCREG_NZ);
647 spsr.c = tc->readCCReg(CCREG_C);
648 spsr.v = tc->readCCReg(CCREG_V);
651 spsr.q = 0;
652 spsr.it1 = 0;
653 spsr.j = 0;
654 spsr.ge = 0;
655 spsr.it2 = 0;
656 spsr
945 CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP); local
1259 CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP); local
1320 CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP); local
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/gem5/src/arch/arm/kvm/
H A Darmv8_cpu.cc107 MiscRegInfo(INT_REG(spsr[KVM_SPSR_EL1]), MISCREG_SPSR_EL1, "SPSR(EL1)"),
108 MiscRegInfo(INT_REG(spsr[KVM_SPSR_ABT]), MISCREG_SPSR_ABT, "SPSR(ABT)"),
109 MiscRegInfo(INT_REG(spsr[KVM_SPSR_UND]), MISCREG_SPSR_UND, "SPSR(UND)"),
110 MiscRegInfo(INT_REG(spsr[KVM_SPSR_IRQ]), MISCREG_SPSR_IRQ, "SPSR(IRQ)"),
111 MiscRegInfo(INT_REG(spsr[KVM_SPSR_FIQ]), MISCREG_SPSR_FIQ, "SPSR(FIQ)"),

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