Searched refs:sequential_access (Results 1 - 8 of 8) sorted by relevance

/gem5/src/mem/cache/tags/
H A DTags.py65 sequential_access = Param.Bool(Parent.sequential_access, variable in class:BaseTags
H A Dbase_set_assoc.cc56 sequentialAccess(p->sequential_access),
H A Dsector_tags.cc52 sequentialAccess(p->sequential_access),
/gem5/src/mem/cache/
H A DCache.py110 sequential_access = Param.Bool(False, variable in class:BaseCache
H A Dbase.cc100 sequentialAccess(p->sequential_access),
/gem5/configs/example/
H A Dmemtest.py311 data_latency = 10, sequential_access = True,
/gem5/configs/dram/
H A Dlat_mem_rd.py272 sequential_access = True variable in class:L3Cache
/gem5/tests/configs/
H A Dbase_config.py287 sequential_access = True,

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