Searched refs:opc2 (Results 1 - 6 of 6) sorted by relevance

/gem5/src/arch/arm/
H A Dmiscregs.cc55 decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) argument
61 switch (opc2) {
73 switch (opc2) {
89 switch (opc2) {
99 switch (opc2) {
113 switch (opc2) {
124 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
125 crn, opc1, crm, opc2);
132 decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) argument
140 switch (opc2) {
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H A Dutility.hh274 uint32_t opc1, uint32_t opc2)
281 (opc2 << 17);
286 uint32_t &crn, uint32_t &opc1, uint32_t &opc2)
293 opc2 = (iss >> 17) & 0x7;
273 mcrMrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, uint32_t crn, uint32_t opc1, uint32_t opc2) argument
285 mcrMrcIssExtract(uint32_t iss, bool &isRead, uint32_t &crm, IntRegIndex &rt, uint32_t &crn, uint32_t &opc1, uint32_t &opc2) argument
H A Dutility.cc469 uint32_t opc2; local
480 mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
610 uint32_t opc2; local
614 mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
616 crm, crn, opc1, opc2, hdcr, hcptr, hstr);
659 uint32_t opc2; local
667 mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
H A Dmiscregs.hh987 unsigned crm, unsigned opc2);
996 unsigned crm, unsigned opc2);
H A Dtypes.hh116 Bitfield<7,5> opc2; member in namespace:ArmISA
/gem5/src/arch/arm/kvm/
H A Darm_cpu.cc105 #define REG_CP32(cpnum, crn, opc1, crm, opc2) ( \
111 ((opc2) << KVM_REG_ARM_32_OPC2_SHIFT))
389 const unsigned opc2(REG_OPC2(id));
394 return decodeCP14Reg(crn, opc1, crm, opc2);
397 return decodeCP15Reg(crn, opc1, crm, opc2);
538 inform("CP%i: [CRn: c%i opc1: %.2i CRm: c%i opc2: %i inv: %i]: "
549 inform("CP%i: [CRn: c%i opc1: %.2i CRm: c%i opc2: %i inv: %i]: [%s]: "
555 inform("CP%i: [CRn: c%i opc1: %.2i CRm: c%i opc2: %i inv: %i "
669 " opc2: %i]\n",
811 " opc2
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