Searched refs:msr (Results 1 - 4 of 4) sorted by relevance

/gem5/system/arm/aarch64_bootloader/
H A Dboot.S54 msr scr_el3, x0
56 msr cptr_el3, xzr // Disable copro. traps to EL3
59 msr cntfrq_el0, x0
96 msr S3_6_C12_C12_5, x10 // write ICC_SRE_EL3
100 msr S3_0_c12_c12_6, x0 // ICC_IGRPEN0_EL1 Enable
101 msr S3_0_C12_C12_7, x0 // ICC_IGRPEN1_EL1 Enable
126 msr sctlr_el2, xzr
133 msr elr_el3, x0
134 msr spsr_el3, x1
185 //msr cntfrq_el
[all...]
/gem5/src/arch/power/
H A Dremote_gdb.hh61 uint32_t msr; member in struct:PowerISA::RemoteGDB::PowerGdbRegCache::__anon5
H A Dremote_gdb.cc190 r.msr = 0; // Is MSR modeled?
/gem5/util/ccdrv/
H A Ddevtime.c43 #include <asm/msr.h>

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