110037SARM gem5 Developers/* 212271Sjose.marinho@arm.com * Copyright (c) 2012 ARM Limited 312271Sjose.marinho@arm.com * All rights reserved 410037SARM gem5 Developers * 512271Sjose.marinho@arm.com * The license below extends only to copyright in the software and shall 612271Sjose.marinho@arm.com * not be construed as granting a license to any other intellectual 712271Sjose.marinho@arm.com * property including but not limited to intellectual property relating 812271Sjose.marinho@arm.com * to a hardware implementation of the functionality of the software 912271Sjose.marinho@arm.com * licensed hereunder. You may use the software subject to the license 1012271Sjose.marinho@arm.com * terms below provided that you ensure that this notice is replicated 1112271Sjose.marinho@arm.com * unmodified and in its entirety in all distributions of the software, 1212271Sjose.marinho@arm.com * modified or unmodified, in source code or in binary form. 1310037SARM gem5 Developers * 1412271Sjose.marinho@arm.com * Redistribution and use in source and binary forms, with or without 1512271Sjose.marinho@arm.com * modification, are permitted provided that the following conditions are 1612271Sjose.marinho@arm.com * met: redistributions of source code must retain the above copyright 1712271Sjose.marinho@arm.com * notice, this list of conditions and the following disclaimer; 1812271Sjose.marinho@arm.com * redistributions in binary form must reproduce the above copyright 1912271Sjose.marinho@arm.com * notice, this list of conditions and the following disclaimer in the 2012271Sjose.marinho@arm.com * documentation and/or other materials provided with the distribution; 2112271Sjose.marinho@arm.com * neither the name of the copyright holders nor the names of its 2212271Sjose.marinho@arm.com * contributors may be used to endorse or promote products derived from 2312271Sjose.marinho@arm.com * this software without specific prior written permission. 2412271Sjose.marinho@arm.com * 2512271Sjose.marinho@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2612271Sjose.marinho@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2712271Sjose.marinho@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2812271Sjose.marinho@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2912271Sjose.marinho@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3012271Sjose.marinho@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3112271Sjose.marinho@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3212271Sjose.marinho@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3312271Sjose.marinho@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3412271Sjose.marinho@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3512271Sjose.marinho@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3612271Sjose.marinho@arm.com * 3710037SARM gem5 Developers */ 3810037SARM gem5 Developers 3910037SARM gem5 Developers .text 4010037SARM gem5 Developers 4110037SARM gem5 Developers .globl _start 4210037SARM gem5 Developers_start: 4310037SARM gem5 Developers /* 4410037SARM gem5 Developers * EL3 initialisation 4510037SARM gem5 Developers */ 4610037SARM gem5 Developers mrs x0, CurrentEL 4710037SARM gem5 Developers cmp x0, #0xc // EL3? 4810037SARM gem5 Developers b.ne start_ns // skip EL3 initialisation 4910037SARM gem5 Developers 5010037SARM gem5 Developers mov x0, #0x30 // RES1 5110037SARM gem5 Developers orr x0, x0, #(1 << 0) // Non-secure EL1 5210037SARM gem5 Developers orr x0, x0, #(1 << 8) // HVC enable 5310037SARM gem5 Developers orr x0, x0, #(1 << 10) // 64-bit EL2 5410037SARM gem5 Developers msr scr_el3, x0 5510037SARM gem5 Developers 5610037SARM gem5 Developers msr cptr_el3, xzr // Disable copro. traps to EL3 5710037SARM gem5 Developers 5810037SARM gem5 Developers ldr x0, =CNTFRQ 5910037SARM gem5 Developers msr cntfrq_el0, x0 6010037SARM gem5 Developers 6110037SARM gem5 Developers /* 6210037SARM gem5 Developers * Check for the primary CPU to avoid a race on the distributor 6310037SARM gem5 Developers * registers. 6410037SARM gem5 Developers */ 6510037SARM gem5 Developers mrs x0, mpidr_el1 6611258Skarthik.sangaiah@arm.com // ARM MPIDR_EL1 bytes: Aff3 (AArch64), Stuff, Aff2, Aff1, Aff0 6711258Skarthik.sangaiah@arm.com // Test the the MPIDR_EL1 register against 0xff00ffffff to 6811258Skarthik.sangaiah@arm.com // extract the primary CPU. 6911258Skarthik.sangaiah@arm.com ldr x1, =0xff00ffffff 7013509Sjairo.balart@metempsy.com#ifdef GICV3 7113509Sjairo.balart@metempsy.com and x2, x0, #0xff // use Aff0 as cpuid for now... 7213509Sjairo.balart@metempsy.com tst x0, x1 // check for cpuid==zero 7313509Sjairo.balart@metempsy.com b.ne 1f // secondary CPU 7413509Sjairo.balart@metempsy.com 7513509Sjairo.balart@metempsy.com ldr x1, =GIC_DIST_BASE // GICD_CTLR 7613509Sjairo.balart@metempsy.com mov w0, #7 // EnableGrp0 | EnableGrp1NS | EnableGrp1S 7713509Sjairo.balart@metempsy.com str w0, [x1] 7813509Sjairo.balart@metempsy.com 7913509Sjairo.balart@metempsy.com 8013509Sjairo.balart@metempsy.com1: ldr x1, =GIC_REDIST_BASE + 0x10000 + 0x80 // GICR_IGROUPR0 8113509Sjairo.balart@metempsy.com // 128K for each redistributor, 256K strided... 8213509Sjairo.balart@metempsy.com mov x3, #1 << 18 // GICv4 8313509Sjairo.balart@metempsy.com mul x3, x3, x2 8413509Sjairo.balart@metempsy.com add x1, x1, x3 8513509Sjairo.balart@metempsy.com mov w0, #~0 // Grp1 interrupts 8613509Sjairo.balart@metempsy.com str w0, [x1], #4 8713509Sjairo.balart@metempsy.com b.ne 2f // Only local interrupts for secondary CPUs 8813509Sjairo.balart@metempsy.com ldr x1, =GIC_DIST_BASE + 0x84 // GICD_IGROUPR 8913509Sjairo.balart@metempsy.com str w0, [x1], #4 9013509Sjairo.balart@metempsy.com str w0, [x1], #4 9113509Sjairo.balart@metempsy.com str w0, [x1], #4 9213509Sjairo.balart@metempsy.com 9314113Schunchenhsu@google.com /* SRE & Disable IRQ/FIQ Bypass & Allow EL2 access to ICC_SRE_EL2 */ 9414113Schunchenhsu@google.com mrs x10, S3_6_C12_C12_5 // read ICC_SRE_EL3 9514113Schunchenhsu@google.com orr x10, x10, #0xf // enable 0xf 9614113Schunchenhsu@google.com msr S3_6_C12_C12_5, x10 // write ICC_SRE_EL3 9714113Schunchenhsu@google.com isb 9813509Sjairo.balart@metempsy.com 9913509Sjairo.balart@metempsy.com2: mov x0, #1 10013509Sjairo.balart@metempsy.com msr S3_0_c12_c12_6, x0 // ICC_IGRPEN0_EL1 Enable 10113509Sjairo.balart@metempsy.com msr S3_0_C12_C12_7, x0 // ICC_IGRPEN1_EL1 Enable 10213509Sjairo.balart@metempsy.com#else 10311258Skarthik.sangaiah@arm.com tst x0, x1 // check for cpuid==zero 10411258Skarthik.sangaiah@arm.com b.ne 1f // secondary CPU 10510037SARM gem5 Developers 10610037SARM gem5 Developers ldr x1, =GIC_DIST_BASE // GICD_CTLR 10710037SARM gem5 Developers mov w0, #3 // EnableGrp0 | EnableGrp1 10810037SARM gem5 Developers str w0, [x1] 10910037SARM gem5 Developers 11010037SARM gem5 Developers1: ldr x1, =GIC_DIST_BASE + 0x80 // GICD_IGROUPR 11110037SARM gem5 Developers mov w0, #~0 // Grp1 interrupts 11210037SARM gem5 Developers str w0, [x1], #4 11310037SARM gem5 Developers b.ne 2f // Only local interrupts for secondary CPUs 11410037SARM gem5 Developers str w0, [x1], #4 11510037SARM gem5 Developers str w0, [x1], #4 11610037SARM gem5 Developers 11710037SARM gem5 Developers2: ldr x1, =GIC_CPU_BASE // GICC_CTLR 11810037SARM gem5 Developers ldr w0, [x1] 11910037SARM gem5 Developers mov w0, #3 // EnableGrp0 | EnableGrp1 12010037SARM gem5 Developers str w0, [x1] 12110037SARM gem5 Developers 12210037SARM gem5 Developers mov w0, #1 << 7 // allow NS access to GICC_PMR 12310037SARM gem5 Developers str w0, [x1, #4] // GICC_PMR 12413509Sjairo.balart@metempsy.com#endif 12510037SARM gem5 Developers 12610037SARM gem5 Developers msr sctlr_el2, xzr 12710037SARM gem5 Developers 12810037SARM gem5 Developers /* 12910037SARM gem5 Developers * Prepare the switch to the EL2_SP1 mode from EL3 13010037SARM gem5 Developers */ 13110037SARM gem5 Developers ldr x0, =start_ns // Return after mode switch 13210037SARM gem5 Developers mov x1, #0x3c9 // EL2_SP1 | D | A | I | F 13310037SARM gem5 Developers msr elr_el3, x0 13410037SARM gem5 Developers msr spsr_el3, x1 13510037SARM gem5 Developers eret 13610037SARM gem5 Developers 13710037SARM gem5 Developersstart_ns: 13810037SARM gem5 Developers /* 13910037SARM gem5 Developers * Kernel parameters 14010037SARM gem5 Developers */ 14110037SARM gem5 Developers mov x0, xzr 14210037SARM gem5 Developers mov x1, xzr 14310037SARM gem5 Developers mov x2, xzr 14410037SARM gem5 Developers mov x3, xzr 14510037SARM gem5 Developers 14610037SARM gem5 Developers mrs x4, mpidr_el1 14711258Skarthik.sangaiah@arm.com // ARM MPIDR_EL1 bytes: Aff3 (AArch64), Stuff, Aff2, Aff1, Aff0 14811258Skarthik.sangaiah@arm.com // Test the the MPIDR_EL1 register against 0xff00ffffff to 14911258Skarthik.sangaiah@arm.com // extract the primary CPU. 15011258Skarthik.sangaiah@arm.com ldr x1, =0xff00ffffff 15111258Skarthik.sangaiah@arm.com tst x4, x1 // check for cpuid==zero 15211258Skarthik.sangaiah@arm.com mov x1, xzr // load previous 'xzr' value back to x1 15311258Skarthik.sangaiah@arm.com b.eq 2f // secondary CPU 15410037SARM gem5 Developers 15510037SARM gem5 Developers /* 15610037SARM gem5 Developers * Secondary CPUs 15710037SARM gem5 Developers */ 15810037SARM gem5 Developers1: wfe 15910037SARM gem5 Developers ldr x4, =PHYS_OFFSET + 0xfff8 16010037SARM gem5 Developers ldr x4, [x4] 16110037SARM gem5 Developers cbz x4, 1b 16210037SARM gem5 Developers br x4 // branch to the given address 16310037SARM gem5 Developers 16410037SARM gem5 Developers2: 16510037SARM gem5 Developers /* 16610037SARM gem5 Developers * UART initialisation (38400 8N1) 16710037SARM gem5 Developers */ 16810037SARM gem5 Developers ldr x4, =UART_BASE // UART base 16910037SARM gem5 Developers mov w5, #0x10 // ibrd 17010037SARM gem5 Developers str w5, [x4, #0x24] 17110037SARM gem5 Developers mov w5, #0xc300 17210037SARM gem5 Developers orr w5, w5, #0x0001 // cr 17310037SARM gem5 Developers str w5, [x4, #0x30] 17410037SARM gem5 Developers 17510037SARM gem5 Developers /* 17610037SARM gem5 Developers * CLCD output site MB 17710037SARM gem5 Developers */ 17810037SARM gem5 Developers ldr x4, =SYSREGS_BASE 17910037SARM gem5 Developers ldr w5, =(1 << 31) | (1 << 30) | (7 << 20) | (0 << 16) // START|WRITE|MUXFPGA|SITE_MB 18010037SARM gem5 Developers str wzr, [x4, #0xa0] // V2M_SYS_CFGDATA 18110037SARM gem5 Developers str w5, [x4, #0xa4] // V2M_SYS_CFGCTRL 18210037SARM gem5 Developers 18310037SARM gem5 Developers // set up the arch timer frequency 18410037SARM gem5 Developers //ldr x0, =CNTFRQ 18510037SARM gem5 Developers //msr cntfrq_el0, x0 18610037SARM gem5 Developers 18710037SARM gem5 Developers /* 18810037SARM gem5 Developers * Primary CPU 18910037SARM gem5 Developers */ 19010037SARM gem5 Developers ldr x0, =PHYS_OFFSET + 0x8000000 // device tree blob 19110037SARM gem5 Developers ldr x6, =PHYS_OFFSET + 0x80000 // kernel start address 19210037SARM gem5 Developers br x6 19310037SARM gem5 Developers 19410037SARM gem5 Developers .ltorg 19510037SARM gem5 Developers 19610037SARM gem5 Developers .org 0x200 197