Searched refs:mainReq (Results 1 - 4 of 4) sorted by relevance

/gem5/src/cpu/
H A Dtranslation.hh70 RequestPtr mainReq; member in class:WholeTranslationState
83 : outstanding(1), delay(false), isSplit(false), mainReq(_req),
98 : outstanding(2), delay(false), isSplit(true), mainReq(_req),
123 mainReq->setPaddr(sreqLow->getPaddr());
125 mainReq->setFlags(sreqLow->getFlags());
126 mainReq->setFlags(sreqHigh->getFlags());
163 return mainReq->isStrictlyOrdered();
174 return mainReq->isPrefetch();
181 return mainReq->getPaddr();
192 return mainReq
[all...]
/gem5/src/cpu/o3/
H A Dlsq_impl.hh818 mainReq->setFlags(req->getFlags());
824 _inst->strictlyOrdered(mainReq->isStrictlyOrdered());
831 _inst->memReqFlags = mainReq->getFlags();
832 if (mainReq->isCondSwap()) {
835 mainReq->setExtraData(*_res);
886 return mainReq;
899 mainReq = std::make_shared<Request>(_inst->getASID(), base_addr,
903 mainReq->setByteEnable(_byteEnable);
906 // Paddr is not used in mainReq. However, we will accumulate the flags
907 // from the sub requests into mainReq b
[all...]
H A Dlsq.hh775 RequestPtr mainReq; member in class:LSQ::LSQRequest::SplitDataRequest
788 mainReq(nullptr),
795 if (mainReq) {
796 mainReq = nullptr;
/gem5/src/cpu/simple/
H A Dtiming.cc641 sendData(state->mainReq, state->data, state->res,
644 sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq,

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