Searched refs:link (Results 1 - 25 of 36) sorted by relevance

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/gem5/ext/googletest/googletest/codegear/
H A Dgtest_link.cc39 #pragma link "gtest.lib"
40 #pragma link "gtest_main.lib"
/gem5/src/python/m5/util/
H A Ddot_writer_ruby.py84 # One link for each direction but draw one edge only
86 for link in network.int_links:
87 if (link.src_node.path() in connected) and \
88 (connected[link.src_node.path()] == link.dst_node.path()):
91 pydot.Edge(link.src_node.path(), link.dst_node.path())
93 connected[link.dst_node.path()] = link.src_node.path()
95 for link i
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/gem5/ext/sst/tests/
H A Dtest6_arm_4c.py113 link = sst.Link("cpu_%s_link"%name)
114 link.connect((m5, connector, lat), (cache, "high_network_0", lat))
119 link = sst.Link("sysbus_bus_link") variable
120 link.connect((SysBusConn, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat))
130 link = sst.Link("ioCache_bus_link") variable
131 link.connect((ioCache, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat))
145 link = sst.Link("cpu%u.l1iCache_bus_link" % num) ; bus_port = bus_port + 1
146 link.connect((l1iCache, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat))
147 link = sst.Link("cpu%u.l1dCache_bus_link" % num) ; bus_port = bus_port + 1
148 link
166 link = sst.Link("l2cache_bus_link") variable
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/gem5/src/mem/ruby/network/simple/
H A DSimpleNetwork.py49 for link in self.int_links:
57 # Also add buffers for all router-link connections
61 # unidirectional internal link
62 for link in self.int_links:
63 if link.dst_node == router:
67 # Add message buffers to routers for each external link connection
68 for link in self.ext_links:
70 if link.int_node in self.routers:
H A DSimpleNetwork.hh62 void makeExtOutLink(SwitchID src, NodeID dest, BasicLink* link,
64 void makeExtInLink(NodeID src, SwitchID dest, BasicLink* link,
66 void makeInternalLink(SwitchID src, SwitchID dest, BasicLink* link,
H A DSimpleNetwork.cc82 SimpleNetwork::makeExtOutLink(SwitchID src, NodeID dest, BasicLink* link, argument
89 SimpleExtLink *simple_link = safe_cast<SimpleExtLink*>(link);
98 SimpleNetwork::makeExtInLink(NodeID src, SwitchID dest, BasicLink* link, argument
107 SimpleNetwork::makeInternalLink(SwitchID src, SwitchID dest, BasicLink* link, argument
124 SimpleIntLink *simple_link = safe_cast<SimpleIntLink*>(link);
H A DSwitch.cc118 for (int link = 0; link < m_throttles.size(); link++) {
119 m_throttles[link]->regStats(name());
/gem5/ext/systemc/src/sysc/utils/
H A Dsc_mempool.cpp82 union link { union in class:sc_core::sc_allocator
83 link* next;
88 // including the link
92 link* free_list;
101 : block_size(sizeof(link) + (((blksz - 1) / cellsz) + 1) * cellsz),
133 link* new_block = (link*) malloc(block_size); // need alignment?
134 new_block->next = (link*) block_list;
136 result = (block_list + sizeof(link));
148 ((link*)
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/gem5/src/mem/ruby/network/garnet2.0/
H A DRoutingUnit.cc71 // First find all possible output link candidates
84 for (int link = 0; link < m_routing_table.size(); link++) {
85 if (msg_destination.intersectionIsNotEmpty(m_routing_table[link])) {
87 if (m_weight_table[link] <= min_weight)
88 min_weight = m_weight_table[link];
93 for (int link = 0; link < m_routing_table.size(); link
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H A DInputUnit.hh130 set_in_link(NetworkLink *link) argument
132 m_in_link = link;
H A DGarnetNetwork.hh91 void makeExtOutLink(SwitchID src, NodeID dest, BasicLink* link,
93 void makeExtInLink(NodeID src, SwitchID dest, BasicLink* link,
95 void makeInternalLink(SwitchID src, SwitchID dest, BasicLink* link,
H A DGarnetNetwork.cc155 * This function creates a link from the Network Interface (NI)
162 GarnetNetwork::makeExtInLink(NodeID src, SwitchID dest, BasicLink* link, argument
167 GarnetExtLink* garnet_link = safe_cast<GarnetExtLink*>(link);
183 * This function creates a link from the Network to a NI.
189 GarnetNetwork::makeExtOutLink(SwitchID src, NodeID dest, BasicLink* link,
196 GarnetExtLink* garnet_link = safe_cast<GarnetExtLink*>(link);
209 link->m_weight, credit_link);
214 * This function creates an internal network link between two routers.
215 * It adds both the network link and an opposite credit link
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/gem5/src/systemc/tests/systemc/compliance_1666/test001/
H A Dtest001.cpp236 Link *link; member in struct:Link
265 Link* link; local
285 link = new Link;
286 link->m = new Mod("mod_1");
287 link->p = new sc_in<int>;
288 link->link = new Link;
289 link->link->m = new Mod("mod_2"); //// Buried dynamic module instantiation DOULOS002
290 link
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/gem5/util/
H A Don-chip-network-power-area.py133 ## Compute the power consumed by the given link
134 def computeLinkPower(link, stats_file, config, sim_seconds):
135 frequency = getClock(link + ".nls0", config)
137 print("%s.nls0 Power: " % link, power)
139 frequency = getClock(link + ".nls1", config)
141 print("%s.nls1 Power: " % link, power)
186 for link in int_links:
187 computeLinkPower(link, stats_file, config,
189 for link in ext_links:
190 computeLinkPower(link, stats_fil
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/gem5/src/base/
H A Dfiber.hh70 /// link points to another fiber which will start executing when this
73 Fiber(Fiber *link, size_t stack_size=DefaultStackSize);
100 /// mark itself as finished and switch to its link fiber.
110 Fiber *link; member in class:Fiber
H A Dfiber.cc89 Fiber::Fiber(Fiber *link, size_t stack_size) : argument
90 link(link), stack(nullptr), stackSize(stack_size), guardPage(nullptr),
158 // main has returned, so this Fiber has finished. Switch to the "link"
161 link->run();
H A Dfiber.test.cc61 StartingFiber(Fiber *link) : Fiber(link) {} argument
154 LinkedFiber(Fiber *link, int index) : Fiber(link), index(index) {} argument
/gem5/src/dev/net/
H A Detherlink.cc45 * Device module for modelling a fixed bandwidth full duplex ethernet link
72 link[0] = new Link(name() + ".link0", this, 0, p->speed,
74 link[1] = new Link(name() + ".link1", this, 1, p->speed,
77 interface[0] = new Interface(name() + ".int0", link[0], link[1]);
78 interface[1] = new Interface(name() + ".int1", link[1], link[0]);
84 delete link[0];
85 delete link[1];
120 link[
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/gem5/configs/topologies/
H A DCluster.py119 link = ExtLink(link_id=self.num_ext_links(), ext_node=node,
123 link.bandwidth_factor = self.intBW
125 link.latency = self.intLatency
127 network.ext_links.append(link)
/gem5/configs/dist/
H A Dsw.py62 for (i, link) in enumerate(switch.portlink):
63 link.int0 = switch.interface[i]
/gem5/ext/sst/
H A DExtSlave.cc59 link(comp->configureLink(name, new Event::Handler<ExtSlave>(this,
62 if (!link) {
63 out.fatal(CALL_INFO, 1, "Failed to configure link %s\n", name.c_str());
72 link->sendInitData(initPackets->front());
130 link->sendInitData(ev);
136 link->send(ev);
/gem5/src/mem/ruby/network/
H A DTopology.cc65 // Thus each external link is converted to two calls to addLink,
103 // create the internal uni-directional link from src to dst
138 BasicLink* link = (*i).second.link; local
141 component_latencies[src][dst] = link->m_latency;
142 topology_weights[src][dst] = link->m_weight;
162 Topology::addLink(SwitchID src, SwitchID dest, BasicLink* link, argument
174 link_entry.link = link;
195 net->makeExtInLink(src, dest - (2 * m_nodes), link_entry.link,
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H A DNetwork.hh101 virtual void makeExtOutLink(SwitchID src, NodeID dest, BasicLink* link,
103 virtual void makeExtInLink(NodeID src, SwitchID dest, BasicLink* link,
105 virtual void makeInternalLink(SwitchID src, SwitchID dest, BasicLink* link,
H A DTopology.hh59 BasicLink *link; member in struct:LinkEntry
77 void addLink(SwitchID src, SwitchID dest, BasicLink* link,
/gem5/src/mem/ruby/slicc_interface/
H A DMessage.hh102 void setIncomingLink(int link) { incoming_link = link; } argument

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