| /gem5/ext/mcpat/cacti/ |
| H A D | mat.cc | 55 is_dram(dyn_p.is_dram),
121 gate_C(g_tp.w_nmos_b_mux, 0, is_dram) + // 2 transistor per cell
129 gate_C(g_tp.w_nmos_sa_mux, 0, is_dram) +
137 gate_C(g_tp.w_nmos_sa_mux, 0, is_dram) +
155 is_dram,
168 is_dram,
177 is_dram,
186 is_dram,
213 is_dram,
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| H A D | decoder.h | 69 bool is_dram; member in class:Decoder
140 bool is_dram);
223 Driver(double c_gate_load_, double c_wire_load_, double r_wire_load_, bool is_dram);
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| H A D | decoder.cc | 61 fully_assoc(fully_assoc_), is_dram(is_dram_),
107 double p_to_n_sz_ratio = pmos_to_nmos_sz_ratio(is_dram, is_wl_tr);
122 F *= C_ld_dec_out / (gate_C(w_dec_n[0], 0, is_dram, false, is_wl_tr) +
123 gate_C(w_dec_p[0], 0, is_dram, false, is_wl_tr));
132 is_dram,
150 cmos_Isub_leakage(w_dec_n[0], w_dec_p[0], 2, nand, is_dram);
152 cmos_Ig_leakage(w_dec_n[0], w_dec_p[0], 2, nand, is_dram);
157 cmos_Isub_leakage(w_dec_n[0], w_dec_p[0], 3, nand, is_dram);;
159 cmos_Ig_leakage(w_dec_n[0], w_dec_p[0], 3, nand, is_dram);
166 cmos_Isub_leakage(w_dec_n[i], w_dec_p[i], 1, inv, is_dram);
264 PredecBlk( int num_dec_signals, Decoder * dec_, double C_wire_predec_blk_out, double R_wire_predec_blk_out_, int num_dec_per_predec, bool is_dram, bool is_blk1) argument
968 PredecBlkDrv( int way_select_, PredecBlk * blk_, bool is_dram) argument
1414 Driver(double c_gate_load_, double c_wire_load_, double r_wire_load_, bool is_dram) argument
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| H A D | mat.h | 110 bool is_dram, is_fa, pure_cam, camFlag; member in class:Mat
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| H A D | parameter.cc | 206 is_dram = ((ram_cell_tech_type == lp_dram) || (ram_cell_tech_type == comm_dram));
224 if ((is_dram) && (!is_tag) && (Ndcm > 1)) {
347 if (is_dram) {
364 if (is_dram) {
518 (PAGE_MODE == 1 && is_dram)) {
576 if (is_dram && is_main_mem) {
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| H A D | uca.cc | 183 if (dp.is_dram) {
223 if (dp.is_dram) {
272 if (dp.is_dram == false) {
385 if (dp.is_dram) {
407 if (dp.is_dram == false) {
413 if (dp.is_dram) {
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| H A D | parameter.h | 315 bool is_dram; member in class:DynamicParameter
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| H A D | subarray.cc | 125 if (dp.is_dram) {
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| H A D | router.cc | 147 dyn_p.is_dram = false;
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| H A D | Ucache.cc | 692 bool is_dram = false; local
733 is_dram = ((ram_cell_tech_type == lp_dram) ||
768 is_dram = ((ram_cell_tech_type == lp_dram) || (ram_cell_tech_type == comm_dram));
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| /gem5/ext/mcpat/ |
| H A D | logic.h | 134 bool is_dram; member in class:DFFCell
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| H A D | logic.cc | 259 : is_dram(_is_dram),
277 Ctotal += drain_C_(WdecNANDn, NCH, 2, 1, g_tp.cell_h_def, is_dram) + fan_in * drain_C_(WdecNANDp, PCH, 1, 1, g_tp.cell_h_def, is_dram);
280 Ctotal += fan_out * gate_C(WdecNANDn + WdecNANDp, 0, is_dram);
295 clock_cap = 2 * gate_C(WdecNANDn + WdecNANDp, 0, is_dram);
823 bool is_dram = false; local
840 C_driver_load = 1024 * gate_C(load_nmos_width + load_pmos_width, 0, is_dram);
849 false/*is_dram*/,
859 false/*is_dram*/,
867 false/*is_dram*/,
[all...] |