mcpat/cacti/mat.cc

55       is_dram(dyn_p.is_dram),
121             gate_C(g_tp.w_nmos_b_mux, 0, is_dram) +  // 2 transistor per cell
129             gate_C(g_tp.w_nmos_sa_mux, 0, is_dram) +
137             gate_C(g_tp.w_nmos_sa_mux, 0, is_dram) +
155         is_dram,
168         is_dram,
177         is_dram,
186         is_dram,
213         is_dram,
221         is_dram,
223     PredecBlk * b_mux_predec_blk1 = new PredecBlk(deg_bl_muxing, bit_mux_dec, 0, 0, 1, is_dram, true);
224     PredecBlk * b_mux_predec_blk2 = new PredecBlk(deg_bl_muxing, bit_mux_dec, 0, 0, 1, is_dram, false);
225     PredecBlk * sa_mux_lev_1_predec_blk1 = new PredecBlk(dyn_p.deg_senseamp_muxing_non_associativity, sa_mux_lev_1_dec, 0, 0, 1, is_dram, true);
226     PredecBlk * sa_mux_lev_1_predec_blk2 = new PredecBlk(dyn_p.deg_senseamp_muxing_non_associativity, sa_mux_lev_1_dec, 0, 0, 1, is_dram, false);
227     PredecBlk * sa_mux_lev_2_predec_blk1 = new PredecBlk(dp.Ndsam_lev_2, sa_mux_lev_2_dec, 0, 0, 1, is_dram, true);
228     PredecBlk * sa_mux_lev_2_predec_blk2 = new PredecBlk(dp.Ndsam_lev_2, sa_mux_lev_2_dec, 0, 0, 1, is_dram, false);
229     dummy_way_sel_predec_blk1 = new PredecBlk(1, sa_mux_lev_1_dec, 0, 0, 0, is_dram, true);
230     dummy_way_sel_predec_blk2 = new PredecBlk(1, sa_mux_lev_1_dec, 0, 0, 0, is_dram, false);
232     PredecBlkDrv * r_predec_blk_drv1 = new PredecBlkDrv(0, r_predec_blk1, is_dram);
233     PredecBlkDrv * r_predec_blk_drv2 = new PredecBlkDrv(0, r_predec_blk2, is_dram);
234     PredecBlkDrv * b_mux_predec_blk_drv1 = new PredecBlkDrv(0, b_mux_predec_blk1, is_dram);
235     PredecBlkDrv * b_mux_predec_blk_drv2 = new PredecBlkDrv(0, b_mux_predec_blk2, is_dram);
236     PredecBlkDrv * sa_mux_lev_1_predec_blk_drv1 = new PredecBlkDrv(0, sa_mux_lev_1_predec_blk1, is_dram);
237     PredecBlkDrv * sa_mux_lev_1_predec_blk_drv2 = new PredecBlkDrv(0, sa_mux_lev_1_predec_blk2, is_dram);
238     PredecBlkDrv * sa_mux_lev_2_predec_blk_drv1 = new PredecBlkDrv(0, sa_mux_lev_2_predec_blk1, is_dram);
239     PredecBlkDrv * sa_mux_lev_2_predec_blk_drv2 = new PredecBlkDrv(0, sa_mux_lev_2_predec_blk2, is_dram);
240     way_sel_drv1 = new PredecBlkDrv(dyn_p.number_way_select_signals_mat, dummy_way_sel_predec_blk1, is_dram);
241     dummy_way_sel_predec_blk_drv2 = new PredecBlkDrv(1, dummy_way_sel_predec_blk2, is_dram);
259                    is_dram, false, false);
268             is_dram);
274                        is_dram, false, false);
283                 is_dram);
288         driver_c_gate_load =  subarray.num_cols * gate_C(2 * g_tp.w_pmos_bl_precharge + g_tp.w_pmos_bl_eq, 0, is_dram, false, false);
295             is_dram);
488             rd = tr_R_on(ml_to_ram_wl_drv->width_n[k], NCH, 1, is_dram, false, true);
490                                    cell.h, is_dram, false, true) +
492                          is_dram, false, true);
498             R_bl_precharge = tr_R_on(g_tp.w_pmos_bl_precharge, PCH, 1, is_dram, false, false);
539             double rd = tr_R_on(row_dec->w_dec_n[k], NCH, 1, is_dram, false, true);
542                                           cell.h, is_dram, false, true) +
543                 drain_C_(row_dec->w_dec_n[k], NCH, 1, 1, 4 * cell.h, is_dram,
549         double R_bl_precharge = tr_R_on(g_tp.w_pmos_bl_precharge, PCH, 1, is_dram, false, false);
554         if (is_dram) {
632                       pmos_to_nmos_sz_ratio(is_dram) * g_tp.min_w_nmos_, cell.w * dp.Ndsam_lev_2 / (RWP + ERP));
690     double p_to_n_sizing_r = pmos_to_nmos_sz_ratio(is_dram);
767     driver_c_gate_load = subarray.num_cols_fa_cam * gate_C(2 * g_tp.w_pmos_bl_precharge + g_tp.w_pmos_bl_eq, 0, is_dram, false, false);
775         is_dram);
779     driver_c_gate_load = (subarray.num_rows + 1) * gate_C(Wdummyn, 0, is_dram, false, false);
786         is_dram);
789     double R_bl_precharge = tr_R_on(g_tp.w_pmos_bl_precharge, PCH, 1, is_dram, false, false);//Assuming CAM and SRAM have same Pre_eq_dr
806     driver_c_gate_load = (subarray.num_rows + 1) * gate_C(Wfaprechp, 0, is_dram);
814         is_dram);
819     rd =  tr_R_on(Wdummyn, NCH, 2, is_dram);
822                       is_dram)//TODO: the cell_h_def should be revisit
823          + drain_C_(Wfaprechp, PCH, 1, 1, g_tp.cell_h_def, is_dram) /
828     c_gate_load = gate_C(Waddrnandn + Waddrnandp, 0, is_dram);
830     double R_ml_precharge = tr_R_on(Wfaprechp, PCH, 1, is_dram);
850     rd = tr_R_on(Waddrnandn, NCH, 2, is_dram);
851     c_intrinsic = drain_C_(Waddrnandn, NCH, 2, 1, g_tp.cell_h_def, is_dram) +
852                   drain_C_(Waddrnandp, PCH, 1, 1, g_tp.cell_h_def, is_dram) * 2;
853     c_gate_load = gate_C(Wdummyinvn + Wdummyinvp, 0, is_dram);
864     rd = tr_R_on(Wdummyinvn, NCH, 1, is_dram);
865     c_intrinsic = drain_C_(Wdummyinvn, NCH, 1, 1, g_tp.cell_h_def, is_dram) + drain_C_(Wdummyinvp, NCH, 1, 1, g_tp.cell_h_def, is_dram);
870     c_gate_load = gate_C(Wfanorn + Wfanorp, 0, is_dram);
882     driver_c_gate_load = gate_C(W_hit_miss_n, 0, is_dram, false, false);//nmos of the pull down logic
890         is_dram);
894     rd = tr_R_on(Wfanorn, NCH, 1, is_dram);
895     c_intrinsic = 2 * drain_C_(Wfanorn, NCH, 1, 1, g_tp.cell_h_def, is_dram) +
896         drain_C_(Wfanorp, NCH, 1, 1, g_tp.cell_h_def, is_dram);
897     c_gate_load = gate_C(ml_to_ram_wl_drv->width_n[0] + ml_to_ram_wl_drv->width_p[0], 0, is_dram);
912         drain_C_(W_hit_miss_p, NCH, 2, 1, g_tp.cell_h_def, is_dram);
915     c_gate_load = drain_C_(W_hit_miss_n, NCH, 1, 1, g_tp.cell_h_def, is_dram) *
918     rd = tr_R_on(W_hit_miss_p, PCH, 1, is_dram, false, false);
928         drain_C_(W_hit_miss_n, NCH, 2, 1, g_tp.cell_h_def, is_dram);
931     c_gate_load = drain_C_(W_hit_miss_n, NCH, 1, 1, g_tp.cell_h_def, is_dram) *
934     rd = tr_R_on(W_hit_miss_n, PCH, 1, is_dram, false, false);
1022     double R_sram_cell_pull_up_tr  = tr_R_on(g_tp.sram.cell_pmos_w, NCH, 1, is_dram, true);
1023     double R_access_tr             = tr_R_on(g_tp.sram.cell_a_w,    NCH, 1, is_dram, true);
1025     double width_write_driver_nmos = R_to_w(target_R_write_driver_and_mux, NCH, is_dram);
1061     if (is_dram == true) {
1106                                       (2 * (RWP + ERP + SCHP)), is_dram);
1107     double R_bit_mux = tr_R_on(g_tp.w_nmos_b_mux, NCH, 1, is_dram);
1111                                             (RWP + ERP + SCHP), is_dram);
1112     double R_sense_amp_iso = tr_R_on(g_tp.w_iso, PCH, 1, is_dram);
1114                                       is_dram) +
1116                  cell.w * deg_bl_muxing / (RWP + ERP + SCHP), is_dram) +
1118                  cell.w * deg_bl_muxing / (RWP + ERP + SCHP), is_dram);
1122                                             (RWP + ERP + SCHP), is_dram);
1124     if (is_dram) {
1225     double Iiso     = simplified_pmos_leakage(g_tp.w_iso, is_dram);
1226     double IsenseEn = simplified_nmos_leakage(g_tp.w_sense_en, is_dram);
1227     double IsenseN  = simplified_nmos_leakage(g_tp.w_sense_n, is_dram);
1228     double IsenseP  = simplified_pmos_leakage(g_tp.w_sense_p, is_dram);
1242     double C_ld = gate_C(g_tp.w_sense_p + g_tp.w_sense_n, 0, is_dram) +
1245                  (RWP + ERP + SCHP), is_dram) +
1248                  is_dram) +
1251                  is_dram) +
1254                  is_dram);
1269     double p_to_n_sz_r = pmos_to_nmos_sz_ratio(is_dram);
1272     rd = tr_R_on(g_tp.w_nmos_sa_mux, NCH, 1, is_dram);
1276                                      is_dram) +
1277         gate_C(g_tp.min_w_nmos_ + p_to_n_sz_r * g_tp.min_w_nmos_, 0.0, is_dram);
1288     rd = tr_R_on(g_tp.min_w_nmos_, NCH, 1, is_dram);
1289     C_ld = drain_C_(g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def, is_dram) +
1290            drain_C_(p_to_n_sz_r * g_tp.min_w_nmos_, PCH, 1, 1, g_tp.cell_h_def, is_dram) +
1291            gate_C(g_tp.min_w_nmos_ + p_to_n_sz_r * g_tp.min_w_nmos_, 0.0, is_dram);
1299                           inv, is_dram) * g_tp.peri_global.Vdd;
1305     rd = tr_R_on(g_tp.min_w_nmos_, NCH, 1, is_dram);
1306     C_ld = drain_C_(g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def, is_dram) +
1308                  is_dram) +
1311                  (RWP + ERP + SCHP), is_dram);
1326     rd = tr_R_on(g_tp.w_nmos_sa_mux, NCH, 1, is_dram);
1330                  is_dram) +
1331            //gate_C(subarray_out_wire->repeater_size * g_tp.min_w_nmos_ * (1 + p_to_n_sz_r), 0.0, is_dram);
1335                (1 + p_to_n_sz_r), 0.0, is_dram);
1358     double Ceq = gate_C(g_tp.w_comp_inv_n2 + g_tp.w_comp_inv_p2, 0, is_dram) +
1359                  drain_C_(g_tp.w_comp_inv_p1, PCH, 1, 1, g_tp.cell_h_def, is_dram) +
1360                  drain_C_(g_tp.w_comp_inv_n1, NCH, 1, 1, g_tp.cell_h_def, is_dram);
1361     double Req = tr_R_on(g_tp.w_comp_inv_p1, PCH, 1, is_dram);
1371                                           is_dram) * 4 * A;
1374                                             is_dram) * 4 * A;
1376     Ceq = gate_C(g_tp.w_comp_inv_n3 + g_tp.w_comp_inv_p3, 0, is_dram) +
1377           drain_C_(g_tp.w_comp_inv_p2, PCH, 1, 1, g_tp.cell_h_def, is_dram) +
1378           drain_C_(g_tp.w_comp_inv_n2, NCH, 1, 1, g_tp.cell_h_def, is_dram);
1379     Req = tr_R_on(g_tp.w_comp_inv_n2, NCH, 1, is_dram);
1385                                     inv, is_dram) * 4 * A;
1387                                       inv, is_dram) * 4 * A;
1390     Ceq = gate_C(g_tp.w_eval_inv_n + g_tp.w_eval_inv_p, 0, is_dram) +
1391           drain_C_(g_tp.w_comp_inv_p3, PCH, 1, 1, g_tp.cell_h_def, is_dram) +
1392           drain_C_(g_tp.w_comp_inv_n3, NCH, 1, 1, g_tp.cell_h_def, is_dram);
1393     Req = tr_R_on(g_tp.w_comp_inv_p3, PCH, 1, is_dram);
1399                                     inv, is_dram) * 4 * A;
1401                                       1, inv, is_dram) * 4 * A;
1404     double r1 = tr_R_on(g_tp.w_comp_n, NCH, 2, is_dram);
1405     double r2 = tr_R_on(g_tp.w_eval_inv_n, NCH, 1, is_dram); /* was switch */
1407                                        g_tp.cell_h_def, is_dram) +
1409                                        g_tp.cell_h_def, is_dram)) +
1410         drain_C_(g_tp.w_eval_inv_p, PCH, 1, 1, g_tp.cell_h_def, is_dram) +
1411         drain_C_(g_tp.w_eval_inv_n, NCH, 1, 1, g_tp.cell_h_def, is_dram);
1413                                        g_tp.cell_h_def, is_dram) +
1415                                        g_tp.cell_h_def, is_dram)) +
1416         drain_C_(g_tp.w_comp_p, PCH, 1, 1, g_tp.cell_h_def, is_dram) +
1417         gate_C(WmuxdrvNANDn + WmuxdrvNANDp, 0, is_dram);
1421                                     inv, is_dram) * 4 * A;
1423                                     is_dram) * 4 * A; // stack factor of 0.2
1426                                       inv, is_dram) * 4 * A;
1429                                       is_dram) * 4 * A;