Searched refs:isIntReg (Results 1 - 11 of 11) sorted by relevance

/gem5/src/arch/power/insts/
H A Dstatic_inst.cc41 if (reg.isIntReg())
/gem5/src/arch/arm/
H A Dutility.hh354 decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx,
364 bool isIntReg; local
367 validReg = decodeMrsMsrBankedReg(sysM, r, isIntReg, regIdx, 0, 0, 0, false);
368 return (validReg && isIntReg) ? regIdx : INTREG_DUMMY;
H A Dutility.cc700 decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx, argument
708 isIntReg = !r;
763 isIntReg = false;
/gem5/src/arch/riscv/
H A Dutility.hh139 if (reg.isIntReg()) {
/gem5/src/cpu/
H A Dreg_class.hh149 bool isIntReg() const { return regClass == IntRegClass; } function in class:RegId
281 bool isIntPhysReg() const { return isIntReg(); }
/gem5/src/cpu/minor/
H A Dexec_context.hh147 assert(reg.isIntReg());
203 assert(reg.isIntReg());
/gem5/src/cpu/simple/
H A Dexec_context.hh182 assert(reg.isIntReg());
192 assert(reg.isIntReg());
/gem5/src/arch/x86/insts/
H A Dstatic_inst.cc137 if (reg.isIntReg()) {
/gem5/src/arch/sparc/insts/
H A Dstatic_inst.cc105 if (reg.isIntReg()) {
/gem5/src/cpu/checker/
H A Dcpu.hh195 assert(reg.isIntReg());
369 assert(reg.isIntReg());
/gem5/src/arch/
H A Disa_parser.py478 def isIntReg(self): member in class:Operand
534 def isIntReg(self): member in class:IntRegOperand
1220 elif op_desc.isIntReg():

Completed in 30 milliseconds