Searched refs:cntrl (Results 1 - 6 of 6) sorted by relevance
/gem5/src/mem/ruby/system/ |
H A D | RubySystem.cc | 87 RubySystem::registerAbstractController(AbstractController* cntrl) argument 89 m_abs_cntrl_vec.push_back(cntrl); 91 MachineID id = cntrl->getMachineID(); 92 m_abstract_controls[id.getType()][id.getNum()] = cntrl; 109 for (int cntrl = 0; cntrl < m_abs_cntrl_vec.size(); cntrl++) { 110 sequencer_map.push_back(m_abs_cntrl_vec[cntrl]->getCPUSequencer()); 112 sequencer_ptr = sequencer_map[cntrl]; 118 for (int cntrl [all...] |
H A D | CacheRecorder.hh | 76 void addRecord(int cntrl, Addr data_addr, Addr pc_addr,
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H A D | CacheRecorder.cc | 152 CacheRecorder::addRecord(int cntrl, Addr data_addr, Addr pc_addr, argument 157 rec->m_cntrl_id = cntrl;
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/gem5/src/mem/ruby/slicc_interface/ |
H A D | AbstractController.hh | 101 virtual void recordCacheTrace(int cntrl, CacheRecorder* tr) = 0;
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/gem5/src/mem/ruby/structures/ |
H A D | CacheMemory.hh | 105 void recordCacheContents(int cntrl, CacheRecorder* tr) const;
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H A D | CacheMemory.cc | 394 CacheMemory::recordCacheContents(int cntrl, CacheRecorder* tr) const 416 tr->addRecord(cntrl, m_cache[i][j]->m_Address,
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