Searched refs:TimingCPUPort (Results 1 - 2 of 2) sorted by relevance

/gem5/src/cpu/simple/
H A Dtiming.hh155 * A TimingCPUPort overrides the default behaviour of the
160 class TimingCPUPort : public MasterPort class in class:TimingSimpleCPU
164 TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu) function in class:TimingSimpleCPU::TimingCPUPort
186 class IcachePort : public TimingCPUPort
191 : TimingCPUPort(_cpu->name() + ".icache_port", _cpu),
214 class DcachePort : public TimingCPUPort
219 : TimingCPUPort(_cpu->name() + ".dcache_port", _cpu),
H A Dtiming.cc73 TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t)

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