Searched refs:MemoryType (Results 1 - 9 of 9) sorted by relevance

/gem5/ext/drampower/src/
H A DMemCommand.cc90 const MemoryType::MemoryType_t& memType = memSpec.memoryType;
94 if (memType == MemoryType::DDR2) {
96 } else if (memType == MemoryType::DDR3) {
98 } else if (memType == MemoryType::DDR4) {
100 } else if (memType == MemoryType::LPDDR) {
102 } else if (memType == MemoryType::LPDDR2) {
104 } else if (memType == MemoryType::LPDDR3) {
106 } else if (memType == MemoryType::WIDEIO_SDR) {
110 if (memType == MemoryType::DDR2) {
112 } else if (memType == MemoryType
[all...]
H A DMemorySpecification.h52 class MemoryType { class in namespace:Data
65 MemoryType(MemoryType_t _val) : function in class:Data::MemoryType
70 MemoryType() : function in class:Data::MemoryType
75 MemoryType(const std::string& _val) : function in class:Data::MemoryType
231 MemoryType memoryType;
H A DCmdScheduler.cc277 if (memSpec.memoryType == MemoryType::DDR4) {
283 if (memSpec.memoryType == MemoryType::DDR4) {
312 if (memSpec.memoryType == MemoryType::WIDEIO_SDR) {
505 case MemoryType::LPDDR:
506 case MemoryType::WIDEIO_SDR:
510 case MemoryType::LPDDR2:
511 case MemoryType::LPDDR3:
516 case MemoryType::DDR2:
522 case MemoryType::DDR3:
523 case MemoryType
[all...]
/gem5/src/arch/arm/
H A Dstage2_lookup.cc115 if (stage2Te->mtype == TlbEntry::MemoryType::StronglyOrdered ||
116 stage1Te.mtype == TlbEntry::MemoryType::StronglyOrdered) {
117 stage1Te.mtype = TlbEntry::MemoryType::StronglyOrdered;
118 } else if (stage2Te->mtype == TlbEntry::MemoryType::Device ||
119 stage1Te.mtype == TlbEntry::MemoryType::Device) {
120 stage1Te.mtype = TlbEntry::MemoryType::Device;
122 stage1Te.mtype = TlbEntry::MemoryType::Normal;
125 if (stage1Te.mtype == TlbEntry::MemoryType::Normal) {
H A Dpagetable.hh89 enum class MemoryType : std::uint8_t { class in struct:ArmISA::TlbEntry
122 MemoryType mtype;
155 domain(DomainType::Client), mtype(MemoryType::StronglyOrdered),
170 domain(DomainType::Client), mtype(MemoryType::StronglyOrdered),
H A Dtable_walker.cc1037 te.mtype = TlbEntry::MemoryType::StronglyOrdered;
1044 te.mtype = TlbEntry::MemoryType::Device;
1050 te.mtype = TlbEntry::MemoryType::Normal;
1056 te.mtype = TlbEntry::MemoryType::Normal;
1063 te.mtype = TlbEntry::MemoryType::Normal;
1075 te.mtype = TlbEntry::MemoryType::Normal;
1082 te.mtype = TlbEntry::MemoryType::Device;
1091 te.mtype = TlbEntry::MemoryType::Normal;
1159 te.mtype = TlbEntry::MemoryType::StronglyOrdered;
1168 te.mtype = TlbEntry::MemoryType
[all...]
H A Dtlb.cc628 (te->mtype != TlbEntry::MemoryType::Normal)) {
638 if (te->mtype != TlbEntry::MemoryType::Normal) {
814 (te->mtype != TlbEntry::MemoryType::Normal)) {
824 if (te->mtype != TlbEntry::MemoryType::Normal) {
1113 temp_te.mtype = is_fetch ? TlbEntry::MemoryType::Normal
1114 : TlbEntry::MemoryType::StronglyOrdered;
1120 temp_te.mtype = TlbEntry::MemoryType::Normal;
1164 if (te->mtype != TlbEntry::MemoryType::Normal)
1174 (te->mtype != TlbEntry::MemoryType::Normal)) {
/gem5/ext/mcpat/cacti/
H A Dparameter.h128 class MemoryType { class in class:TechnologyParameter
231 MemoryType sram;
232 MemoryType dram;
233 MemoryType cam;
H A Dparameter.cc89 void TechnologyParameter::MemoryType::display(uint32_t indent) {

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