Searched refs:MSTATUS_TSR (Results 1 - 2 of 2) sorted by relevance

/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64mi/
H A Dillegal.S180 li t1, MSTATUS_TSR
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h24 #define MSTATUS_TSR 0x00400000 macro

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