Searched refs:MISCREG_SPSR_SVC (Results 1 - 6 of 6) sorted by relevance

/gem5/src/arch/arm/
H A Dutility.cc722 regIdx = MISCREG_SPSR_SVC;
H A Disa.hh575 flat_idx = MISCREG_SPSR_SVC;
H A Dmiscregs.hh62 MISCREG_SPSR_SVC, enumerator in enum:ArmISA::MiscRegIndex
H A Dfaults.cc579 tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr);
H A Dmiscregs.cc2901 InitReg(MISCREG_SPSR_SVC)
4071 .mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1
/gem5/src/arch/arm/kvm/
H A Darm_cpu.cc237 { REG_CORE32(svc_regs[2]), MISCREG_SPSR_SVC, "SPSR(SVC)" },

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