Searched refs:MISCREG_PERFCNT0 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/mips/
H A Dregisters.hh237 MISCREG_PERFCNT0 = 200, //Bank 25: 200-207 enumerator in enum:MipsISA::MiscRegIndex
H A Disa.cc301 PerfCntCtlReg perfCntCtl = readMiscRegNoEffect(MISCREG_PERFCNT0);
304 setMiscRegNoEffect(MISCREG_PERFCNT0, perfCntCtl);
308 setRegMask(MISCREG_PERFCNT0, pc_Mask);

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