Searched refs:MISCREG_ICV_DIR_EL1 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/arm/
H A Dmiscregs.hh778 MISCREG_ICV_DIR_EL1, enumerator in enum:ArmISA::MiscRegIndex
/gem5/src/dev/arm/
H A Dgic_v3_cpu_interface.cc941 return setMiscReg(MISCREG_ICV_DIR_EL1, val);
1020 case MISCREG_ICV_DIR_EL1: {

Completed in 20 milliseconds