Searched refs:MISCREG_ICH_AP1R0_EL2 (Results 1 - 3 of 3) sorted by relevance

/gem5/src/dev/arm/
H A Dgic_v3_cpu_interface.cc643 case MISCREG_ICH_AP1R0_EL2:
1589 case MISCREG_ICH_AP1R0_EL2:
1744 RegVal vapr1 = isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i);
1759 isa->setMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i, vapr1);
1869 MISCREG_ICH_AP0R0_EL2 + reg_no : MISCREG_ICH_AP1R0_EL2 + reg_no;
2194 isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i);
/gem5/src/arch/arm/
H A Dmiscregs.hh730 MISCREG_ICH_AP1R0_EL2, enumerator in enum:ArmISA::MiscRegIndex
H A Dmiscregs.cc2493 return MISCREG_ICH_AP1R0_EL2;
4689 InitReg(MISCREG_ICH_AP1R0_EL2)

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