Searched refs:MISCREG_ICC_IGRPEN0_EL1 (Results 1 - 3 of 3) sorted by relevance

/gem5/src/dev/arm/
H A Dgic_v3_cpu_interface.cc169 case MISCREG_ICC_IGRPEN0_EL1: {
1325 case MISCREG_ICC_IGRPEN0_EL1: {
1330 isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1, val);
2303 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1);
/gem5/src/arch/arm/
H A Dmiscregs.hh716 MISCREG_ICC_IGRPEN0_EL1, enumerator in enum:ArmISA::MiscRegIndex
H A Dmiscregs.cc2455 return MISCREG_ICC_IGRPEN0_EL1;
4644 InitReg(MISCREG_ICC_IGRPEN0_EL1)

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