Searched refs:MISCREG_ICC_BPR1_EL1_NS (Results 1 - 3 of 3) sorted by relevance

/gem5/src/arch/arm/
H A Dmiscregs.hh708 MISCREG_ICC_BPR1_EL1_NS, enumerator in enum:ArmISA::MiscRegIndex
H A Dmiscregs.cc4608 InitReg(MISCREG_ICC_BPR1_EL1_NS)
/gem5/src/dev/arm/
H A Dgic_v3_cpu_interface.cc1084 isa->setMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_NS, val);
2565 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_NS);

Completed in 31 milliseconds