Searched refs:MISCREG_CP0_RANDOM (Results 1 - 2 of 2) sorted by relevance
| /gem5/src/arch/mips/ | ||
| H A D | registers.hh | 138 MISCREG_CP0_RANDOM = 8, //Bank 1: 8 - 15 enumerator in enum:MipsISA::MiscRegIndex |
| H A D | isa.cc | 311 setMiscRegNoEffect(MISCREG_CP0_RANDOM, 63); 315 setRegMask(MISCREG_CP0_RANDOM, random_Mask); |
Completed in 11 milliseconds