Searched refs:GICR_ISPENDR0 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/dev/arm/
H A Dgic_v3_redistributor.hh117 GICR_ISPENDR0 = SGI_base + 0x0200, enumerator in enum:Gicv3Redistributor::__anon10
H A Dgic_v3_redistributor.cc247 case GICR_ISPENDR0: // Interrupt Set-Pending Register 0
496 case GICR_ISPENDR0: // Interrupt Set-Pending Register 0
509 "(GICR_ISPENDR0): int_id %d (PPI) "

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