Searched refs:GICR_ICENABLER0 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/dev/arm/
H A Dgic_v3_redistributor.hh115 GICR_ICENABLER0 = SGI_base + 0x0180, enumerator in enum:Gicv3Redistributor::__anon10
H A Dgic_v3_redistributor.cc228 case GICR_ICENABLER0: { // Interrupt Clear-Enable Register 0
475 case GICR_ICENABLER0: // Interrupt Clear-Enable Register 0

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