Searched refs:GICR_CTLR (Results 1 - 2 of 2) sorted by relevance

/gem5/src/dev/arm/
H A Dgic_v3_redistributor.hh79 GICR_CTLR = RD_base + 0x0000, enumerator in enum:Gicv3Redistributor::__anon9
H A Dgic_v3_redistributor.cc116 case GICR_CTLR: { // Control Register
152 * (GICR_CTLR.DPG* bits are supported)
413 case GICR_CTLR: {
896 // GICR_CTLR.EnableLPIs == 0.

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