Searched refs:GICD_ISENABLER (Results 1 - 5 of 5) sorted by relevance

/gem5/src/dev/arm/
H A Dgic_v3_distributor.hh103 static const AddrRange GICD_ISENABLER; member in class:Gicv3Distributor
H A Dgic_v2.cc55 const AddrRange GicV2::GICD_ISENABLER (0x100, 0x17f);
177 if (GICD_ISENABLER.contains(daddr)) {
178 uint32_t ix = (daddr - GICD_ISENABLER.start()) >> 2;
434 if (GICD_ISENABLER.contains(daddr)) {
435 uint32_t ix = (daddr - GICD_ISENABLER.start()) >> 2;
H A Dgic_v3_distributor.cc54 const AddrRange Gicv3Distributor::GICD_ISENABLER (0x0100, 0x017f);
160 } else if (GICD_ISENABLER.contains(addr)) {
163 int first_intid = (addr - GICD_ISENABLER.start()) * 8;
530 } else if (GICD_ISENABLER.contains(addr)) {
532 int first_intid = (addr - GICD_ISENABLER.start()) * 8;
H A Dgic_v2.hh83 static const AddrRange GICD_ISENABLER; // interrupt set enable member in class:GicV2
/gem5/src/arch/arm/kvm/
H A Dgic.cc360 set = GicV2::GICD_ISENABLER.start();

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