Searched refs:GICD_ICFGR (Results 1 - 5 of 5) sorted by relevance

/gem5/src/dev/arm/
H A Dgic_v3_distributor.hh119 static const AddrRange GICD_ICFGR; member in class:Gicv3Distributor
H A Dgic_v2.cc63 const AddrRange GicV2::GICD_ICFGR (0xc00, 0xcff);
254 if (GICD_ICFGR.contains(daddr)) {
255 uint32_t ix = (daddr - GICD_ICFGR.start()) >> 2;
526 if (GICD_ICFGR.contains(daddr)) {
527 uint32_t ix = (daddr - GICD_ICFGR.start()) >> 2;
H A Dgic_v3_distributor.cc62 const AddrRange Gicv3Distributor::GICD_ICFGR (0x0c00, 0x0cff);
333 } else if (GICD_ICFGR.contains(addr)) {
335 int first_intid = (addr - GICD_ICFGR.start()) * 4;
733 } else if (GICD_ICFGR.contains(addr)) {
736 // GICD_ICFGR[2x] = RES0
737 // GICD_ICFGR[2x + 1] =
740 int first_intid = (addr - GICD_ICFGR.start()) * 4;
H A Dgic_v2.hh91 static const AddrRange GICD_ICFGR; // interrupt config registers member in class:GicV2
117 /** Mask for bits that config N:N mode in GICD_ICFGR's */
/gem5/src/arch/arm/kvm/
H A Dgic.cc406 set = GicV2::GICD_ICFGR.start();

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