Searched refs:GICC_IAR (Results 1 - 3 of 3) sorted by relevance
| /gem5/src/dev/arm/ | ||
| H A D | gic_v2.hh | 98 GICC_IAR = 0x0C, // interrupt ack register enumerator in enum:GicV2::__anon123 |
| H A D | gic_v3_cpu_interface.hh | 169 GICC_IAR = 0x000C, enumerator in enum:Gicv3CPUInterface::__anon5 |
| H A D | gic_v2.cc | 320 case GICC_IAR: 902 * writes GICD_ICPENDR or reads GICC_IAR */ |
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