Searched refs:GICC_EOIR (Results 1 - 3 of 3) sorted by relevance
| /gem5/src/dev/arm/ | ||
| H A D | gic_v2.hh | 99 GICC_EOIR = 0x10, // end of interrupt enumerator in enum:GicV2::__anon123 |
| H A D | gic_v3_cpu_interface.hh | 170 GICC_EOIR = 0x0010, enumerator in enum:Gicv3CPUInterface::__anon5 |
| H A D | gic_v2.cc | 592 case GICC_EOIR: { |
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