Searched refs:Complete (Results 1 - 8 of 8) sorted by relevance

/gem5/src/cpu/minor/
H A Dfetch1.hh96 * become Complete). Responses can be picked up from the head of the
118 Complete /* Complete. Either a fault, or a fetched line */ enumerator in enum:Minor::Fetch1::FetchRequest::FetchRequestState
154 bool isComplete() const { return state == Complete; }
H A Dlsq.cc99 DPRINTFS(MinorMem, (&port), "Complete disabled mem access for inst:%s\n",
174 return state == Complete;
239 case LSQ::LSQRequest::Complete:
240 os << "Complete";
278 setState(Complete);
313 setState(LSQ::LSQRequest::Complete);
323 setState(Complete);
362 setState(Complete);
603 setState(LSQ::LSQRequest::Complete);
664 /* Complete earl
[all...]
H A Dlsq.hh182 Complete enumerator in enum:Minor::LSQ::LSQRequest::LSQRequestState
335 { state = Complete; }
702 /** Complete a barrier instruction. Where committed, makes a
H A Dfetch1.cc299 * as Complete/packet == NULL */
301 request->state = FetchRequest::Complete;
432 fetch_request->state = FetchRequest::Complete;
/gem5/src/cpu/o3/
H A Dlsq.hh251 Complete = 0x00000100,
583 return flags.isSet(Flag::Complete);
684 flags.set(Flag::Complete);
H A Dlsq_impl.hh990 flags.set(Flag::Complete);
1009 flags.set(Flag::Complete);
/gem5/ext/testlib/
H A Drunner.py127 self.testable.status = Status.Complete
H A Dhandlers.py127 if record['status'] in (state.Status.Complete, state.Status.Avoided):

Completed in 26 milliseconds