Searched refs:CAUSE_MISALIGNED_FETCH (Results 1 - 3 of 3) sorted by relevance

/gem5/tests/test-progs/asmtest/src/riscv/env/p/
H A Driscv_test.h159 (1 << CAUSE_MISALIGNED_FETCH) | \
/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64si/
H A Dma_fetch.S132 li a1, CAUSE_MISALIGNED_FETCH
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h962 #define CAUSE_MISALIGNED_FETCH 0x0 macro
1456 DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)

Completed in 14 milliseconds