Searched refs:base (Results 76 - 100 of 167) sorted by relevance

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/gem5/src/arch/x86/
H A Dsystem.cc47 #include "base/loader/object_file.hh"
100 tc->setMiscReg(MISCREG_SEG_BASE(seg), desc.base);
101 tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), honorBase ? desc.base : 0);
158 initDesc.base = 0;
249 Addr base = 0; local
254 uint64_t pdte = X86ISA::htog(0x87 | base);
256 base += pageSize;
/gem5/src/base/loader/
H A Dsymtab.hh39 #include "base/types.hh"
79 void serialize(const std::string &base, CheckpointOut &cp) const;
80 void unserialize(const std::string &base, CheckpointIn &cp);
/gem5/src/arch/x86/insts/
H A Dmicroldstop.hh60 const RegIndex base; member in class:X86ISA::MemOp
78 scale(_scale), index(_index.index()), base(_base.index()),
H A Dstatic_inst.cc232 uint8_t scale, RegIndex index, RegIndex base,
249 if (base != ZeroReg)
253 printReg(os, InstRegIndex(base), addressSize);
231 printMem(std::ostream &os, uint8_t segment, uint8_t scale, RegIndex index, RegIndex base, uint64_t disp, uint8_t addressSize, bool rip) const argument
/gem5/src/dev/storage/
H A Dide_ctrl.hh40 #include "base/bitunion.hh"
117 void serialize(const std::string &base, std::ostream &os) const;
118 void unserialize(const std::string &base, CheckpointIn &cp);
/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64ui/
H A Dsb.S32 # Test with a negative base
42 # Test with unaligned base
H A Dsd.S32 # Test with a negative base
42 # Test with unaligned base
H A Dsh.S32 # Test with a negative base
42 # Test with unaligned base
H A Dsw.S32 # Test with a negative base
42 # Test with unaligned base
/gem5/src/mem/cache/compressors/
H A Dbdi.hh43 #include "base/types.hh"
44 #include "mem/cache/compressors/base.hh"
80 * combination of base and delta size. Otherwise, just create a
81 * compressor for each base size with the highest available delta
127 * @tparam TB Type of a base entry.
218 * The index is given relative to 64-bit entries, therefore if the base
220 * joins multiple base-delta entries to generate the respective 64-bit
278 uint64_t base; member in class:BDI::BDICompDataRep
350 * @tparam TB Type of a base entry.
378 * Add a base t
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/gem5/ext/dnet/
H A Dblob.h15 u_char *base; /* start of data */ member in struct:blob
/gem5/src/base/
H A Dbitunion.hh39 #include "base/bitfield.hh"
57 "Bitfield base class must be empty.");
269 operator<(Base const &base) const
271 return Base::__storage < base.__storage;
275 operator==(Base const &base) const
277 return Base::__storage == base.__storage;
291 //Finally, the base storage is defined which BitfieldOperators will refer to
405 //An STL style hash structure for hashing BitUnions based on their base type.
H A Dcprintf_formats.hh48 enum { dec, hex, oct } base; member in struct:cp::Format
66 base = dec;
93 switch (fmt.base) {
111 switch (fmt.base) {
/gem5/util/style/
H A Dsort_includes.py126 the same base name, but a header extension)."""
139 base, ext = m.groups()
142 if fname == "%s.%s" % (base, header_map[ext]):
316 for base in args:
317 for filename,language in find_files(base, languages=opts.languages,
/gem5/src/base/stats/
H A Dhdf5.cc40 #include "base/stats/hdf5.hh"
42 #include "base/logging.hh"
43 #include "base/stats/info.hh"
105 auto base = path.top(); local
111 group = base.openGroup(name);
113 group = base.createGroup(name);
115 group = base.createGroup(name);
/gem5/ext/pybind11/include/pybind11/
H A Dattr.h39 template <typename T> struct base { struct
40 PYBIND11_DEPRECATED("base<T>() was deprecated in favor of specifying 'T' as a template argument to class_")
41 base() { } function in struct:base
233 /// List of base classes of the newly created type
257 PYBIND11_NOINLINE void add_base(const std::type_info &base, void *(*caster)(void *)) { argument
258 auto base_info = detail::get_type_info(base, false);
260 std::string tname(base.name());
263 "\" referenced unknown base type \"" + tname + "\"");
267 std::string tname(base.name());
271 " a non-default holder type while its base \""
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/gem5/src/arch/arm/insts/
H A Dstatic_inst.hh50 #include "base/trace.hh"
65 int32_t shift_rm_imm(uint32_t base, uint32_t shamt,
67 int32_t shift_rm_rs(uint32_t base, uint32_t shamt,
70 bool shift_carry_imm(uint32_t base, uint32_t shamt,
72 bool shift_carry_rs(uint32_t base, uint32_t shamt,
75 int64_t shiftReg64(uint64_t base, uint64_t shiftAmt,
77 int64_t extendReg64(uint64_t base, ArmExtendType type,
H A Dmem64.hh51 IntRegIndex base; member in class:ArmISA::SysDC64
58 base(_base), dest(_dest), imm(_imm)
97 IntRegIndex base; member in class:ArmISA::Memory64
98 /// True if the base register is SP (used for SP alignment checking).
107 dest(_dest), base(_base), uops(NULL), memAccessFlags(0)
/gem5/system/alpha/console/
H A Dprintf.c140 power(long base, long n) argument
145 p = p * base;
/gem5/ext/libelf/
H A Dlibelf_ar.c74 * number in the specified base.
77 _libelf_ar_get_number(char *s, size_t sz, int base, size_t *ret) argument
83 assert(base <= 10);
98 if (v >= base) /* Illegal digit. */
100 r *= base;
/gem5/ext/testlib/
H A Dresult.py141 def output_path(test_uid, suite_uid, base=None):
146 if base is None:
147 base = config.result_path
149 base,
/gem5/util/
H A Dgit-pre-commit.py84 verifiers = [ v(ui, opts, base=repo_base) for v in all_verifiers ]
/gem5/util/m5/
H A Dm5.c120 uint8_t *base = buf; local
123 ret = write(dest_fid, base, len);
133 base += ret;
/gem5/tests/test-progs/asmtest/src/riscv/isa/macros/scalar/
H A Dtest_macros.h218 #define TEST_LD_OP( testnum, inst, result, offset, base ) \
220 la x1, base; \
224 #define TEST_ST_OP( testnum, load_inst, store_inst, result, offset, base ) \
226 la x1, base; \
232 #define TEST_LD_DEST_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
236 1: la x1, base; \
246 #define TEST_LD_SRC1_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
250 1: la x1, base; \
259 #define TEST_ST_SRC12_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
265 la x2, base; \
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/gem5/src/arch/alpha/
H A Dstacktrace.cc37 #include "base/bitfield.hh"
38 #include "base/trace.hh"
39 #include "cpu/base.hh"
79 Addr base = ksp & ~0x3fff; local
80 if (base == ULL(0xfffffc0000000000))
86 tsk = vp.read<Addr>(base + task_off, GuestByteOrder);

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