/gem5/src/base/filters/ |
H A D | h3_bloom_filter.cc | 375 H3::hash(Addr addr, int hash_number) const 378 bits(addr, std::numeric_limits<Addr>::digits - 1, offsetBits);
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/gem5/src/dev/x86/ |
H A D | I8042.py | 41 data_port = Param.Addr('Data port address') 42 command_port = Param.Addr('Command/status port address')
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/gem5/src/cpu/pred/ |
H A D | bpred_unit.hh | 98 virtual void uncondBranch(ThreadID tid, Addr pc, void * &bp_history) = 0; 142 virtual bool lookup(ThreadID tid, Addr instPC, void * &bp_history) = 0; 152 virtual void btbUpdate(ThreadID tid, Addr instPC, void * &bp_history) = 0; 159 bool BTBValid(Addr instPC) 167 TheISA::PCState BTBLookup(Addr instPC) 183 virtual void update(ThreadID tid, Addr instPC, bool taken, 186 Addr corrTarget = MaxAddr) = 0; 192 void BTBUpdate(Addr instPC, const TheISA::PCState &target) 204 PredictorHistory(const InstSeqNum &seq_num, Addr instPC, 223 Addr p [all...] |
H A D | tage_base.hh | 139 Addr branchPC; 189 virtual int bindex(Addr pc_in) const; 199 virtual int gindex(ThreadID tid, Addr pc, int bank) const; 217 virtual uint16_t gtag(ThreadID tid, Addr pc, int bank) const; 245 virtual bool getBimodePred(Addr pc, BranchInfo* bi) const; 254 void baseUpdate(Addr pc, bool taken, BranchInfo* bi); 276 void update(ThreadID tid, Addr branch_pc, bool taken, BranchInfo* bi); 291 ThreadID tid, Addr branch_pc, bool taken, BranchInfo* b, 294 Addr target = MaxAddr); 310 ThreadID tid, bool taken, BranchInfo *bi, Addr targe [all...] |
/gem5/src/arch/sparc/ |
H A D | pagetable.hh | 46 VAddr(Addr a) { panic("not implemented yet."); } 68 Addr va() const { assert(populated); return bits(entry,41,0); } 160 Addr size() const { assert(_size() < 6); return pageSizes[_size()]; } 161 Addr sizeMask() const { return size() - 1; } 163 Addr pfn() const { assert(populated); return bits(entry4u,39,13); } 164 Addr paddr() const { assert(populated); return mbits(entry4u, 39,13);} 172 Addr paddrMask() const { assert(populated); return paddr() & ~sizeMask(); } 174 Addr 175 translate(Addr vaddr) const 178 Addr mas [all...] |
/gem5/src/arch/arm/insts/ |
H A D | misc.cc | 46 MrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 129 MsrImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 138 MsrRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 148 MrrcOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 161 McrrOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 174 ImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 183 RegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 193 RegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 204 RegRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 218 RegRegRegRegOp::generateDisassembly(Addr p [all...] |
/gem5/src/cpu/ |
H A D | profile.hh | 48 typedef std::map<Addr, ProfileNode *> ChildList; 69 std::map<Addr, Counter> pc_count; 77 ProfileNode *consume(const std::vector<Addr> &stack); 80 void sample(ProfileNode *node, Addr pc);
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H A D | decode_cache.hh | 53 /// A sparse map from an Addr to a Value, stored in page chunks. 63 typedef typename std::unordered_map<Addr, CachePage *> PageMap; 83 getPage(Addr addr) 85 Addr page_addr = addr & ~(TheISA::PageBytes - 1); 122 lookup(Addr addr)
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/gem5/src/arch/power/insts/ |
H A D | floating.cc | 36 FloatOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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H A D | misc.cc | 36 MiscOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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H A D | misc.hh | 53 Addr pc, const SymbolTable *symtab) const override;
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/gem5/src/arch/x86/bios/ |
H A D | E820.py | 46 addr = Param.Addr(0, 'address of the beginning of the region')
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/gem5/src/base/loader/ |
H A D | hex_file.hh | 48 void parseLine(char *, Addr *, uint32_t *);
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/gem5/src/kern/freebsd/ |
H A D | events.hh | 60 UDelayEvent(PCEventQueue *q, const std::string &desc, Addr addr,
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/gem5/src/mem/ruby/common/ |
H A D | SubBlock.hh | 42 SubBlock(Addr addr, int size); 45 Addr getAddress() const { return m_address; } 46 void setAddress(Addr addr) { m_address = addr; } 69 Addr m_address;
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/gem5/src/cpu/testers/directedtest/ |
H A D | DirectedGenerator.hh | 46 virtual void performCallback(uint32_t proc, Addr address) = 0;
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/gem5/src/kern/linux/ |
H A D | events.hh | 54 DebugPrintkEvent(PCEventQueue *q, const std::string &desc, Addr addr) 73 DmesgDumpEvent(PCEventQueue *q, const std::string &desc, Addr addr, 93 KernelPanicEvent(PCEventQueue *q, const std::string &desc, Addr addr, 119 UDelayEvent(PCEventQueue *q, const std::string &desc, Addr addr,
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/gem5/src/arch/x86/insts/ |
H A D | microfpop.cc | 56 std::string FpOp::generateDisassembly(Addr pc,
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/gem5/src/arch/alpha/ |
H A D | kernel_stats.hh | 54 Addr idleProcess; 88 void context(Addr oldpcbb, Addr newpcbb, ThreadContext *tc); 93 void setIdleProcess(Addr idle, ThreadContext *tc);
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/gem5/src/arch/sparc/insts/ |
H A D | priv.cc | 40 Priv::generateDisassembly(Addr pc, const SymbolTable *symtab) const 50 RdPriv::generateDisassembly(Addr pc, const SymbolTable *symtab) const 63 WrPriv::generateDisassembly(Addr pc, const SymbolTable *symtab) const 83 WrPrivImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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H A D | trap.cc | 38 Trap::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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H A D | unknown.hh | 59 generateDisassembly(Addr pc, const SymbolTable *symtab) const override
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H A D | priv.hh | 50 Addr pc, const SymbolTable *symtab) const override; 71 Addr pc, const SymbolTable *symtab) const override; 81 Addr pc, const SymbolTable *symtab) const override; 110 Addr pc, const SymbolTable *symtab) const override;
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/gem5/src/arch/riscv/insts/ |
H A D | compressed.cc | 44 CompRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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/gem5/src/arch/generic/ |
H A D | decode_cache.hh | 58 TheISA::ExtMachInst mach_inst, Addr addr);
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