Searched hist:9961 (Results 1 - 9 of 9) sorted by relevance

/gem5/tests/configs/
H A Drealview-switcheroo-atomic.py9961:1991dd858e47 Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> test: Use SimpleMemory for atomic full-system tests

Keep it simple and use the SimpleMemory rather than the DRAM
controller model for atomic full-system tests.
H A Dpc-simple-atomic.py9961:1991dd858e47 Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> test: Use SimpleMemory for atomic full-system tests

Keep it simple and use the SimpleMemory rather than the DRAM
controller model for atomic full-system tests.
H A Drealview-simple-atomic-dual.py9961:1991dd858e47 Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> test: Use SimpleMemory for atomic full-system tests

Keep it simple and use the SimpleMemory rather than the DRAM
controller model for atomic full-system tests.
H A Drealview-simple-atomic.py9961:1991dd858e47 Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> test: Use SimpleMemory for atomic full-system tests

Keep it simple and use the SimpleMemory rather than the DRAM
controller model for atomic full-system tests.
H A Dtsunami-simple-atomic-dual.py9961:1991dd858e47 Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> test: Use SimpleMemory for atomic full-system tests

Keep it simple and use the SimpleMemory rather than the DRAM
controller model for atomic full-system tests.
H A Dtsunami-simple-atomic.py9961:1991dd858e47 Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> test: Use SimpleMemory for atomic full-system tests

Keep it simple and use the SimpleMemory rather than the DRAM
controller model for atomic full-system tests.
/gem5/src/mem/cache/
H A Dcache.cc12730:6c2ea88bf129 Mon Apr 16 09:36:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: Create an address aware TempCacheBlk

tempBlock has its member variables manually set in order to allow
it to be used in the block address regeneration function. This is
not necessary, and ti can be simply given the address, so it does
not need to be aware of set and tag. This will simplify
implementation of sector and skewed caches.

Change-Id: Iaffb10c323509722cd5589fe1030b818d43336d6
Reviewed-on: https://gem5-review.googlesource.com/9961
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
H A Dbase.hh12730:6c2ea88bf129 Mon Apr 16 09:36:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: Create an address aware TempCacheBlk

tempBlock has its member variables manually set in order to allow
it to be used in the block address regeneration function. This is
not necessary, and ti can be simply given the address, so it does
not need to be aware of set and tag. This will simplify
implementation of sector and skewed caches.

Change-Id: Iaffb10c323509722cd5589fe1030b818d43336d6
Reviewed-on: https://gem5-review.googlesource.com/9961
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
H A Dbase.cc12730:6c2ea88bf129 Mon Apr 16 09:36:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: Create an address aware TempCacheBlk

tempBlock has its member variables manually set in order to allow
it to be used in the block address regeneration function. This is
not necessary, and ti can be simply given the address, so it does
not need to be aware of set and tag. This will simplify
implementation of sector and skewed caches.

Change-Id: Iaffb10c323509722cd5589fe1030b818d43336d6
Reviewed-on: https://gem5-review.googlesource.com/9961
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

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