Searched hist:9676 (Results 1 - 2 of 2) sorted by relevance
| /gem5/src/mem/ | ||
| H A D | page_table.cc | 9676:83d5112e71dd Tue Apr 23 09:47:00 EDT 2013 Mitch Hayenga <mitch.hayenga+gem5@gmail.com> sim: Fix two bugs relating to software caching of PageTable entries. The existing implementation can read uninitialized data or stale information from the cached PageTable entries. 1) Add a valid bit for the cache entries. Simply using zero for the virtual address to signify invalid entries is not sufficient. Speculative, wrong-path accesses frequently access page zero. The current implementation would return a uninitialized TLB entry when address zero was accessed and the PageTable cache entry was invalid. 2) When unmapping/mapping/remaping a page, invalidate the corresponding PageTable cache entry if one already exists. |
| H A D | page_table.hh | 9676:83d5112e71dd Tue Apr 23 09:47:00 EDT 2013 Mitch Hayenga <mitch.hayenga+gem5@gmail.com> sim: Fix two bugs relating to software caching of PageTable entries. The existing implementation can read uninitialized data or stale information from the cached PageTable entries. 1) Add a valid bit for the cache entries. Simply using zero for the virtual address to signify invalid entries is not sufficient. Speculative, wrong-path accesses frequently access page zero. The current implementation would return a uninitialized TLB entry when address zero was accessed and the PageTable cache entry was invalid. 2) When unmapping/mapping/remaping a page, invalidate the corresponding PageTable cache entry if one already exists. |
Completed in 24 milliseconds