Searched hist:8374 (Results 1 - 2 of 2) sorted by relevance
| /gem5/src/arch/sparc/ | ||
| H A D | tlb.cc | 8374:18173b099ed1 Sun Jun 19 21:43:00 EDT 2011 Korey Sewell <ksewell@umich.edu> sparc: init. cache state in TLB valgrind complains and its a potential source of instability, so go ahead and set it to 0 to start |
| /gem5/src/cpu/o3/ | ||
| H A D | iew_impl.hh | 12537:aeff8f3d80c9 Tue Feb 13 14:01:00 EST 2018 Andreas Sandberg <andreas.sandberg@arm.com> cpu-o3: Don't add non-speculative mem barriers to the IQ twice There are cases where the IEW adds a non-speculative instruction to the IQ twice. This can happen if an instruction is flagged as IsMemBarrier and IsNonSpeculative. Avoid adding non-speculative instructions in the IEW to the IQ by checking if it has been added already. Change-Id: Ifcff676a451b57b2406ce00ed8dae19ed399515f Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Javier Setoain <javier.setoain@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8374 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
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