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| /gem5/configs/common/ | ||
| H A D | Options.py | 8671:7945abdd05cb Tue Jan 10 07:35:00 EST 2012 Nilay Vaish <nilay@cs.wisc.edu> Config: Remove short option string for cpu type |
| /gem5/src/cpu/simple/ | ||
| H A D | timing.hh | 7945:32758425de8c Fri Feb 11 19:29:00 EST 2011 Ali Saidi <Ali.Saidi@ARM.com> SimpleCPU: Fix a case where a DTLB fault redirects fetch and an I-side walk occurs. This change fixes an issue where a DTLB fault occurs and redirects fetch to handle the fault and the ITLB requires a walk which delays translation. In this case the status of the cpu isn't updated appropriately, and an additional instruction fetch occurs. Eventually this hits an assert as multiple instruction fetches are occuring in the system and when the second one returns the processor is in the wrong state. Some asserts below are removed because it was always true (typo) and the state after the initiateAcc() the processor could be in any valid state when a d-side fault occurs. |
| H A D | timing.cc | 7945:32758425de8c Fri Feb 11 19:29:00 EST 2011 Ali Saidi <Ali.Saidi@ARM.com> SimpleCPU: Fix a case where a DTLB fault redirects fetch and an I-side walk occurs. This change fixes an issue where a DTLB fault occurs and redirects fetch to handle the fault and the ITLB requires a walk which delays translation. In this case the status of the cpu isn't updated appropriately, and an additional instruction fetch occurs. Eventually this hits an assert as multiple instruction fetches are occuring in the system and when the second one returns the processor is in the wrong state. Some asserts below are removed because it was always true (typo) and the state after the initiateAcc() the processor could be in any valid state when a d-side fault occurs. |
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