Searched hist:5362 (Results 1 - 3 of 3) sorted by relevance
| /gem5/src/arch/arm/insts/ | ||
| H A D | pseudo.cc | 12260:91f39e81ac12 Mon Oct 23 05:49:00 EDT 2017 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Writes to DCCMVAC shouldn't flush pipeline Writes to DCCMVAC (Data Cache line Clean by VA to PoC) system register shouldn't flush the pipeline as a result of the operation. This addition was wrongly introduced for supporting self-modifying code. Software barriers should be used instead. Change-Id: Idf0c27d2e49ca01be19888ae5523b8f8eaefa7b3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5362 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/cpu/o3/ | ||
| H A D | free_list.hh | 5362:0adba9a562c9 Wed Feb 27 16:48:00 EST 2008 Korey Sewell <ksewell@umich.edu> Fix offset in removeThread() function so that float registers start freeing up from the right point (#32 usually) instead of restarting at 0 and double-freeing. Commented out assert line in free_list.hh that will check for when double-free condition goes bad. |
| H A D | cpu.cc | 5362:0adba9a562c9 Wed Feb 27 16:48:00 EST 2008 Korey Sewell <ksewell@umich.edu> Fix offset in removeThread() function so that float registers start freeing up from the right point (#32 usually) instead of restarting at 0 and double-freeing. Commented out assert line in free_list.hh that will check for when double-free condition goes bad. |
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