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/gem5/util/statetrace/base/
H A Darch_check.h8117:2eec3c58e50e Thu Mar 03 01:53:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Statetrace: Rename i386 to i686.
8116:7739ad28c365 Thu Mar 03 01:53:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Statetrace: Fix the i686 detection macro.
8113:5c7c804e0645 Thu Mar 03 01:53:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Statetrace: Accomodate cross compiling statetrace with scons.
H A Dtracechild.hh8113:5c7c804e0645 Thu Mar 03 01:53:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Statetrace: Accomodate cross compiling statetrace with scons.
H A Dstatetrace.cc8114:04b349c6dbf9 Thu Mar 03 01:53:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Statetrace: Tweak the help for the -nt option.
8113:5c7c804e0645 Thu Mar 03 01:53:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Statetrace: Accomodate cross compiling statetrace with scons.
H A Dregstate.hh8113:5c7c804e0645 Thu Mar 03 01:53:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Statetrace: Accomodate cross compiling statetrace with scons.
H A Dtracechild.cc8113:5c7c804e0645 Thu Mar 03 01:53:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Statetrace: Accomodate cross compiling statetrace with scons.
/gem5/src/arch/arm/
H A DSConsopts6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5
/gem5/util/statetrace/
H A DSConscript8113:5c7c804e0645 Thu Mar 03 01:53:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Statetrace: Accomodate cross compiling statetrace with scons.
H A DSConstruct8117:2eec3c58e50e Thu Mar 03 01:53:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Statetrace: Rename i386 to i686.
8113:5c7c804e0645 Thu Mar 03 01:53:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Statetrace: Accomodate cross compiling statetrace with scons.
8112:70fffada3270 Thu Mar 03 01:53:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Statetrace: Convert the build to scons.
/gem5/util/vi/
H A Dvimrc10952:fca6a566f057 Fri Jul 31 22:53:00 EDT 2015 Anthony Gutierrez <atgutier@umich.edu> util: add a vimrc that matches gem5 style guide
/gem5/util/statetrace/arch/i686/
H A Dtracechild.cc8118:92229cb0cee9 Thu Mar 03 01:53:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Statetrace: Stub out the missing i386 version of sendState.
8117:2eec3c58e50e Thu Mar 03 01:53:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Statetrace: Rename i386 to i686.
H A Dtracechild.hh8118:92229cb0cee9 Thu Mar 03 01:53:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Statetrace: Stub out the missing i386 version of sendState.
8117:2eec3c58e50e Thu Mar 03 01:53:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Statetrace: Rename i386 to i686.
/gem5/src/arch/arm/isa/
H A Dcopyright.txt6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5
H A Dmain.isa6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5
/gem5/util/statetrace/arch/amd64/
H A Dtracechild.hh8113:5c7c804e0645 Thu Mar 03 01:53:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Statetrace: Accomodate cross compiling statetrace with scons.
H A Dtracechild.cc8113:5c7c804e0645 Thu Mar 03 01:53:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Statetrace: Accomodate cross compiling statetrace with scons.
/gem5/util/statetrace/arch/sparc/
H A Dtracechild.hh8113:5c7c804e0645 Thu Mar 03 01:53:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Statetrace: Accomodate cross compiling statetrace with scons.
H A Dtracechild.cc8113:5c7c804e0645 Thu Mar 03 01:53:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Statetrace: Accomodate cross compiling statetrace with scons.
/gem5/util/statetrace/arch/arm/
H A Dtracechild.hh8113:5c7c804e0645 Thu Mar 03 01:53:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Statetrace: Accomodate cross compiling statetrace with scons.
H A Dtracechild.cc8113:5c7c804e0645 Thu Mar 03 01:53:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Statetrace: Accomodate cross compiling statetrace with scons.
/gem5/src/arch/arm/isa/formats/
H A Dbasic.isa6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5
/gem5/src/mem/slicc/ast/
H A DVarExprAST.py10972:53d63eeee46f Mon Jul 20 10:15:00 EDT 2015 David Hashe <david.hashe@amd.com> slicc: support for arbitrary DPRINTF flags (not just RubySlicc)

This patch allows DPRINTFs to be used in SLICC state machines similar to how
they are used by the rest of gem5. Previously all DPRINTFs in the .sm files
had to use the RubySlicc flag.
/gem5/src/sim/
H A Dsyscall_emul_buf.hh10498:91b05b34b074 Wed Oct 22 18:53:00 EDT 2014 Steve Reinhardt <steve.reinhardt@amd.com> syscall_emul: devirtualize BaseBufferArg methods

Not clear why they were marked virtual to begin with,
but that doesn't appear to be necessary.
10497:73a59d5e0923 Wed Oct 22 18:53:00 EDT 2014 Steve Reinhardt <steve.reinhardt@amd.com> syscall_emul: Put BufferArg classes in a separate header.

Move the BufferArg classes that support syscall buffer args
(i.e., pointers into simulated user space) out of syscall_emul.hh
and into a new header syscall_emul_buf.hh so they are accessible
to emulated driver implementations.

Take the opportunity to add some comments as well.
/gem5/src/arch/x86/isa/decoder/
H A Dthree_byte_0f38_opcodes.isa10593:a39de7b8d2c9 Thu Dec 04 18:53:00 EST 2014 Gabe Black <gabeblack@google.com> x86: Rework opcode parsing to support 3 byte opcodes properly.

Instead of counting the number of opcode bytes in an instruction and recording
each byte before the actual opcode, we can represent the path we took to get to
the actual opcode byte by using a type code. That has a couple of advantages.
First, we can disambiguate the properties of opcodes of the same length which
have different properties. Second, it reduces the amount of data stored in an
ExtMachInst, making them slightly easier/faster to create and process. This
also adds some flexibility as far as how different types of opcodes are
handled, which might come in handy if we decide to support VEX or XOP
instructions.

This change also adds tables to support properly decoding 3 byte opcodes.
Before we would fall off the end of some arrays, on top of the ambiguity
described above.

This change doesn't measureably affect performance on the twolf benchmark.
H A Dthree_byte_0f3a_opcodes.isa10593:a39de7b8d2c9 Thu Dec 04 18:53:00 EST 2014 Gabe Black <gabeblack@google.com> x86: Rework opcode parsing to support 3 byte opcodes properly.

Instead of counting the number of opcode bytes in an instruction and recording
each byte before the actual opcode, we can represent the path we took to get to
the actual opcode byte by using a type code. That has a couple of advantages.
First, we can disambiguate the properties of opcodes of the same length which
have different properties. Second, it reduces the amount of data stored in an
ExtMachInst, making them slightly easier/faster to create and process. This
also adds some flexibility as far as how different types of opcodes are
handled, which might come in handy if we decide to support VEX or XOP
instructions.

This change also adds tables to support properly decoding 3 byte opcodes.
Before we would fall off the end of some arrays, on top of the ambiguity
described above.

This change doesn't measureably affect performance on the twolf benchmark.
/gem5/util/
H A Dcscope-index.py12043:55cd1129e41b Thu Feb 23 15:53:00 EST 2017 Gedare Bloom <gedare@rtems.org> util: generate fully qualified paths for cscope

Change-Id: I318c185b117b9608110544526fbaaa3fdcdeb8bc
Signed-off-by: Gedare Bloom <gedare@rtems.org>
Reviewed-on: https://gem5-review.googlesource.com/3260
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

Completed in 27 milliseconds

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