Searched hist:53 (Results 76 - 100 of 402) sorted by relevance
/gem5/src/arch/x86/isa/microops/ | ||
H A D | microops.isa | 4524:f051dcff22b3 Mon Jun 04 15:53:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make limm (load immediate) microop |
/gem5/src/arch/arm/linux/ | ||
H A D | linux.cc | 6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5 |
H A D | process.hh | 6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5 |
/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ | ||
H A D | simout | 9183:8ee71266699b Wed Sep 05 21:53:00 EDT 2012 Joel Hestness <hestness@cs.wisc.edu> stats: Update Ruby regressions for memory controller fix |
/gem5/src/arch/x86/ | ||
H A D | types.cc | 10593:a39de7b8d2c9 Thu Dec 04 18:53:00 EST 2014 Gabe Black <gabeblack@google.com> x86: Rework opcode parsing to support 3 byte opcodes properly. Instead of counting the number of opcode bytes in an instruction and recording each byte before the actual opcode, we can represent the path we took to get to the actual opcode byte by using a type code. That has a couple of advantages. First, we can disambiguate the properties of opcodes of the same length which have different properties. Second, it reduces the amount of data stored in an ExtMachInst, making them slightly easier/faster to create and process. This also adds some flexibility as far as how different types of opcodes are handled, which might come in handy if we decide to support VEX or XOP instructions. This change also adds tables to support properly decoding 3 byte opcodes. Before we would fall off the end of some arrays, on top of the ambiguity described above. This change doesn't measureably affect performance on the twolf benchmark. |
/gem5/src/arch/x86/isa/ | ||
H A D | bitfields.isa | 10593:a39de7b8d2c9 Thu Dec 04 18:53:00 EST 2014 Gabe Black <gabeblack@google.com> x86: Rework opcode parsing to support 3 byte opcodes properly. Instead of counting the number of opcode bytes in an instruction and recording each byte before the actual opcode, we can represent the path we took to get to the actual opcode byte by using a type code. That has a couple of advantages. First, we can disambiguate the properties of opcodes of the same length which have different properties. Second, it reduces the amount of data stored in an ExtMachInst, making them slightly easier/faster to create and process. This also adds some flexibility as far as how different types of opcodes are handled, which might come in handy if we decide to support VEX or XOP instructions. This change also adds tables to support properly decoding 3 byte opcodes. Before we would fall off the end of some arrays, on top of the ambiguity described above. This change doesn't measureably affect performance on the twolf benchmark. |
/gem5/src/arch/x86/isa/decoder/ | ||
H A D | decoder.isa | 10593:a39de7b8d2c9 Thu Dec 04 18:53:00 EST 2014 Gabe Black <gabeblack@google.com> x86: Rework opcode parsing to support 3 byte opcodes properly. Instead of counting the number of opcode bytes in an instruction and recording each byte before the actual opcode, we can represent the path we took to get to the actual opcode byte by using a type code. That has a couple of advantages. First, we can disambiguate the properties of opcodes of the same length which have different properties. Second, it reduces the amount of data stored in an ExtMachInst, making them slightly easier/faster to create and process. This also adds some flexibility as far as how different types of opcodes are handled, which might come in handy if we decide to support VEX or XOP instructions. This change also adds tables to support properly decoding 3 byte opcodes. Before we would fall off the end of some arrays, on top of the ambiguity described above. This change doesn't measureably affect performance on the twolf benchmark. |
/gem5/src/arch/generic/ | ||
H A D | SConscript | 9020:14321ce30881 Fri May 25 03:53:00 EDT 2012 Gabe Black <gblack@eecs.umich.edu> Decode: Make the Decoder class defined per ISA. |
/gem5/src/mem/ruby/common/ | ||
H A D | Consumer.cc | 9600:34df8f24be7e Fri Mar 22 16:53:00 EDT 2013 Nilay Vaish <nilay@cs.wisc.edu> ruby: consumer: avoid using receiver side clock A set of patches was recently committed to allow multiple clock domains in ruby. In those patches, I had inadvertently made an incorrect use of the clocks. Suppose object A needs to schedule an event on object B. It was possible that A accesses B's clock to schedule the event. This is not possible in actual system. Hence, changes are being to the Consumer class so as to avoid such happenings. Note that in a multi eventq simulation, this can possibly lead to an incorrect simulation. There are two functions in the Consumer class that are used for scheduling events. The first function takes in the relative delay over the current time as the argument and adds the current time to it for scheduling the event. The second function takes in the absolute time (in ticks) for scheduling the event. The first function is now being moved to protected section of the class so that only objects of the derived classes can use it. All other objects will have to specify absolute time while scheduling an event for some consumer. |
/gem5/src/arch/ | ||
H A D | micro_asm.py | 4591:f275f155962a Tue Jun 19 13:53:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make an error message a little more descriptive. |
/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/ | ||
H A D | interrupts_and_exceptions.py | 5434:2f6dad874e14 Thu Jun 12 00:53:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Implement a partial, sort of correct version of the protected mode variant of iret. |
/gem5/src/systemc/core/ | ||
H A D | sc_interface.cc | 13041:ffcb5efb97d7 Tue Aug 07 07:53:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: "Implement" sc_interface's methods. Most don't do anything. Make default_event() return a dummy event to avoid dereferencing a null pointer. Change-Id: I8d6d576d3a1f585029c387cd414bbebf2d670644 Reviewed-on: https://gem5-review.googlesource.com/12072 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
/gem5/src/arch/arm/ | ||
H A D | stage2_lookup.hh | 10537:47fe87b0cf97 Fri Nov 14 03:53:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> arm: Fixes based on UBSan and static analysis Another churn to clean up undefined behaviour, mostly ARM, but some parts also touching the generic part of the code base. Most of the fixes are simply ensuring that proper intialisation. One of the more subtle changes is the return type of the sign-extension, which is changed to uint64_t. This is to avoid shifting negative values (undefined behaviour) in the ISA code. |
/gem5/src/cpu/minor/ | ||
H A D | fetch1.hh | 10537:47fe87b0cf97 Fri Nov 14 03:53:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> arm: Fixes based on UBSan and static analysis Another churn to clean up undefined behaviour, mostly ARM, but some parts also touching the generic part of the code base. Most of the fixes are simply ensuring that proper intialisation. One of the more subtle changes is the return type of the sign-extension, which is changed to uint64_t. This is to avoid shifting negative values (undefined behaviour) in the ISA code. |
/gem5/src/mem/cache/replacement_policies/ | ||
H A D | base.hh | 12684:44ebd2bc020f Tue Mar 27 05:53:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: ReplacementPolicy specific replacement data Replacement data is specific for each replacement policy, and thus should be instantiated differently by each policy. Touch() and reset() do not need to be aware of CacheBlk, as they only update its ReplacementData. Invalidate() makes replacement policies independent of cache blocks, by removing the awareness of the valid state. An inheritable base ReplaceableEntry class was created to allow usage of replacement policies with any table-like structure. Change-Id: I998917d800fa48504ed95abffa2f1b7bfd68522b Reviewed-on: https://gem5-review.googlesource.com/9421 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
H A D | lru_rp.hh | 12684:44ebd2bc020f Tue Mar 27 05:53:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: ReplacementPolicy specific replacement data Replacement data is specific for each replacement policy, and thus should be instantiated differently by each policy. Touch() and reset() do not need to be aware of CacheBlk, as they only update its ReplacementData. Invalidate() makes replacement policies independent of cache blocks, by removing the awareness of the valid state. An inheritable base ReplaceableEntry class was created to allow usage of replacement policies with any table-like structure. Change-Id: I998917d800fa48504ed95abffa2f1b7bfd68522b Reviewed-on: https://gem5-review.googlesource.com/9421 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
/gem5/src/sim/power/ | ||
H A D | mathexpr_powermodel.cc | 11972:9503a0d8c352 Thu Apr 06 09:53:00 EDT 2017 Stephan Diestelhorst <stephan.diestelhorst@arm.com> power: Allow global stats in power equations Allow global stats such as sim_seconds in power equations to make it possible to convert from event stats to rate stats. Change-Id: I429abe0ffadc0dbd162eb39e0897143be472ef65 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2720 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
/gem5/configs/ruby/ | ||
H A D | GPU_VIPER_Region.py | 12598:b80b2d9a251b Mon Feb 12 10:53:00 EST 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> arch-arm, configs: Treat the bootloader rom as cacheable memory Prior to this changeset the bootloader rom (instantiated as a SimpleMemory) in ruby Arm systems was treated as an IO device and it was fronted by a DMA controller. This changeset moves the bootloader rom and adds it to the system as another memory with a dedicated directory controller. Change-Id: I094fed031cdef7f77a939d94f948d967b349b7e0 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8741 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
H A D | GPU_VIPER_Baseline.py | 12598:b80b2d9a251b Mon Feb 12 10:53:00 EST 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> arch-arm, configs: Treat the bootloader rom as cacheable memory Prior to this changeset the bootloader rom (instantiated as a SimpleMemory) in ruby Arm systems was treated as an IO device and it was fronted by a DMA controller. This changeset moves the bootloader rom and adds it to the system as another memory with a dedicated directory controller. Change-Id: I094fed031cdef7f77a939d94f948d967b349b7e0 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8741 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
H A D | Garnet_standalone.py | 12598:b80b2d9a251b Mon Feb 12 10:53:00 EST 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> arch-arm, configs: Treat the bootloader rom as cacheable memory Prior to this changeset the bootloader rom (instantiated as a SimpleMemory) in ruby Arm systems was treated as an IO device and it was fronted by a DMA controller. This changeset moves the bootloader rom and adds it to the system as another memory with a dedicated directory controller. Change-Id: I094fed031cdef7f77a939d94f948d967b349b7e0 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8741 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
/gem5/src/arch/sparc/ | ||
H A D | decoder.hh | 9020:14321ce30881 Fri May 25 03:53:00 EDT 2012 Gabe Black <gblack@eecs.umich.edu> Decode: Make the Decoder class defined per ISA. |
/gem5/src/python/ | ||
H A D | importer.py | 7502:3ef7ff12c788 Wed Jul 21 18:53:00 EDT 2010 Nathan Binkert <nate@binkert.org> python: Add mechanism to override code compiled into the exectuable If the user sets the environment variable M5_OVERRIDE_PY_SOURCE to True, then imports that would normally find python code compiled into the executable will instead first check in the absolute location where the code was found during the build of the executable. This only works for files in the src (or extras) directories, not automatically generated files. This is a developer feature! |
/gem5/src/python/m5/ | ||
H A D | debug.py | 12008:af9e577f8eac Mon May 08 11:53:00 EDT 2017 Andreas Sandberg <andreas.sandberg@arm.com> python: Fix debug flag listing regression The PyBind11 changes slightly modified gem5's internal debug interfaces. The corresponding change to the public API went missing before the new bindings were merged. This change updates the Python glue to use the new interface. Change-Id: I3ecca5a3f6c35b99d55126d697371124f81a12dd Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3140 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
/gem5/src/arch/arm/isa/insts/ | ||
H A D | sve_mem.isa | 14106:293e3f4b1321 Wed Apr 04 11:53:00 EDT 2018 Javier Setoain <javier.setoain@arm.com> arch-arm: Add support for SVE load/store structures Change-Id: I4d9cde18dfc3d478eacc156de6a4a9721eb9e2ff Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13524 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
/gem5/src/arch/arm/isa/templates/ | ||
H A D | sve_mem.isa | 14106:293e3f4b1321 Wed Apr 04 11:53:00 EDT 2018 Javier Setoain <javier.setoain@arm.com> arch-arm: Add support for SVE load/store structures Change-Id: I4d9cde18dfc3d478eacc156de6a4a9721eb9e2ff Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13524 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
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