Searched hist:4115 (Results 1 - 6 of 6) sorted by relevance
/gem5/src/mem/ | ||
H A D | packet_access.hh | 4115:cc1d6df13c7d Fri Mar 02 22:34:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way as the twin 64 bit loads src/arch/isa_parser.py: src/arch/sparc/isa/decoder.isa: src/arch/sparc/isa/operands.isa: src/base/bigint.hh: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: src/mem/packet_access.hh: make ldtw(a) Twin 32 bit load work correctly |
/gem5/src/arch/sparc/isa/ | ||
H A D | operands.isa | 4115:cc1d6df13c7d Fri Mar 02 22:34:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way as the twin 64 bit loads src/arch/isa_parser.py: src/arch/sparc/isa/decoder.isa: src/arch/sparc/isa/operands.isa: src/base/bigint.hh: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: src/mem/packet_access.hh: make ldtw(a) Twin 32 bit load work correctly |
H A D | decoder.isa | 4115:cc1d6df13c7d Fri Mar 02 22:34:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way as the twin 64 bit loads src/arch/isa_parser.py: src/arch/sparc/isa/decoder.isa: src/arch/sparc/isa/operands.isa: src/base/bigint.hh: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: src/mem/packet_access.hh: make ldtw(a) Twin 32 bit load work correctly |
/gem5/src/arch/ | ||
H A D | isa_parser.py | 4115:cc1d6df13c7d Fri Mar 02 22:34:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way as the twin 64 bit loads src/arch/isa_parser.py: src/arch/sparc/isa/decoder.isa: src/arch/sparc/isa/operands.isa: src/base/bigint.hh: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: src/mem/packet_access.hh: make ldtw(a) Twin 32 bit load work correctly |
/gem5/src/cpu/simple/ | ||
H A D | timing.cc | 4115:cc1d6df13c7d Fri Mar 02 22:34:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way as the twin 64 bit loads src/arch/isa_parser.py: src/arch/sparc/isa/decoder.isa: src/arch/sparc/isa/operands.isa: src/base/bigint.hh: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: src/mem/packet_access.hh: make ldtw(a) Twin 32 bit load work correctly |
H A D | atomic.cc | 4115:cc1d6df13c7d Fri Mar 02 22:34:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way as the twin 64 bit loads src/arch/isa_parser.py: src/arch/sparc/isa/decoder.isa: src/arch/sparc/isa/operands.isa: src/base/bigint.hh: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: src/mem/packet_access.hh: make ldtw(a) Twin 32 bit load work correctly |
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