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/gem5/src/arch/sparc/isa/
H A Ddecoder.isa3765:4035cb300ce9 Wed Dec 06 05:43:00 EST 2006 Gabe Black <gblack@eecs.umich.edu> Some basic fix ups, and CWP is no longer set explicitly.
/gem5/src/cpu/o3/
H A Dcommit.hh4035:f80ad98b2304 Fri Mar 23 13:13:00 EDT 2007 Kevin Lim <ktlim@umich.edu> Updates for commit.
1. Move interrupt handling to a separate function to clean up main commit() function a bit. Also gate the function call off properly based on whether or not there are outstanding interrupts, and the system is not in PAL mode.
2. Better handling of updating instruction's status bits. Instructions are not marked "atCommit" until other stages view it (pushed off to IEW/IQ), and they have been properly handled (faults).
3. Don't consider the ROB "empty" for the purpose of other stages until the ROB is empty, all stores have written back, and there was no store commits this cycle. The last is necessary in case a store committed, in which case it would look like all stores have written back but in actuality have not.

src/cpu/o3/commit.hh:
Slightly modify how interrupts are handled. Also include some extra bools to keep track of state properly.
src/cpu/o3/commit_impl.hh:
Slightly modify how interrupts are handled. Also include some extra bools to keep track of state.

General correctness updates, most specifically for when commit broadcasts to other stages that the ROB is empty.
H A Dcommit_impl.hh4035:f80ad98b2304 Fri Mar 23 13:13:00 EDT 2007 Kevin Lim <ktlim@umich.edu> Updates for commit.
1. Move interrupt handling to a separate function to clean up main commit() function a bit. Also gate the function call off properly based on whether or not there are outstanding interrupts, and the system is not in PAL mode.
2. Better handling of updating instruction's status bits. Instructions are not marked "atCommit" until other stages view it (pushed off to IEW/IQ), and they have been properly handled (faults).
3. Don't consider the ROB "empty" for the purpose of other stages until the ROB is empty, all stores have written back, and there was no store commits this cycle. The last is necessary in case a store committed, in which case it would look like all stores have written back but in actuality have not.

src/cpu/o3/commit.hh:
Slightly modify how interrupts are handled. Also include some extra bools to keep track of state properly.
src/cpu/o3/commit_impl.hh:
Slightly modify how interrupts are handled. Also include some extra bools to keep track of state.

General correctness updates, most specifically for when commit broadcasts to other stages that the ROB is empty.

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