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/gem5/src/mem/
H A Dphysical.cc3281:d0f7a2e1573f Thu Oct 12 13:33:00 EDT 2006 Ron Dreslinski <rdreslin@umich.edu> Fix problems with unCacheable addresses in timing-coherence

src/base/traceflags.py:
src/mem/physical.cc:
Add debug falgs fro physical memory accesses
src/mem/cache/cache_impl.hh:
Snoops to uncacheable blocks should not happen
src/mem/cache/miss/miss_queue.cc:
Set the size properly on unCacheable accesses

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