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| /gem5/src/mem/cache/ | ||
| H A D | cache.hh | 2826:d20db4a6f7d1 Fri Jun 30 16:25:00 EDT 2006 Ron Dreslinski <rdreslin@umich.edu> First pass, now compiles with current head of tree. Compile and initialization work, still working on functionality. src/mem/cache/base_cache.cc: Temp fix for cpu's use of getPort functionality. CPU's will need to be ported to the new connector objects. Also, all packets have to have data or the delete fails. src/mem/cache/cache.hh: Fix function prototypes so overloading works src/mem/cache/cache_impl.hh: fix functions to match virtual base class src/mem/cache/miss/miss_queue.cc: Packets havve to have data, or delete fails src/python/m5/objects/BaseCache.py: Update for newmem |
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