Searched hist:2011 (Results 76 - 100 of 897) sorted by relevance

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/gem5/src/arch/power/
H A Dmiscregs.hh7811:a8fc35183c10 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Make commenting on close namespace brackets consistent.

Ran all the source files through 'perl -pi' with this script:

s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|;
s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|;
s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|;

Also did a little manual editing on some of the arch/*/isa_traits.hh files
and src/SConscript.
H A Dstacktrace.cc8792:1c0812bae427 Sun Nov 13 03:40:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Power: Add a stubbed out stacktrace.cc
H A DSConscript8792:1c0812bae427 Sun Nov 13 03:40:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Power: Add a stubbed out stacktrace.cc
8772:a5a83fc04972 Sun Oct 30 06:55:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Remove the last references to FULL_SYSTEM from POWER.
8759:e9455f81588f Sun Oct 16 08:06:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Power: Add a stub implementation for vtophys in SE and FS.
8745:575cab0db076 Sun Oct 09 03:15:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Build the Interrupt objects in SE mode.
8335:9228e00459d4 Thu Jun 02 20:36:00 EDT 2011 Nathan Binkert <nate@binkert.org> scons: rename TraceFlags to DebugFlags
/gem5/src/arch/x86/
H A Dstacktrace.hh8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
H A Dvtophys.cc8768:314eb1e2fa94 Sun Oct 30 03:33:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> X86: Get rid of more uses of FULL_SYSTEM.
8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
7924:20dc73b1d980 Mon Feb 07 04:21:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> X86: Fix compiling vtophys.cc
7901:f9b675da608a Mon Feb 07 01:14:00 EST 2011 Joel Hestness <hestness@cs.utexas.edu> x86: implements vtophys

Calls walker to look up virt. to phys. page mapping
/gem5/util/
H A Dcheckpoint_aggregator.py8166:c40d598146ec Sun Mar 20 00:12:00 EDT 2011 Lisa Hsu <Lisa.Hsu@amd.com> util: update aggregator to handle x86 checkpoints.
Also, make update to understand some of the newer serialized variables
/gem5/src/arch/x86/regs/
H A Dmsr.hh8582:dd79a696b91c Fri Sep 23 05:42:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> X86: Move the MSR lookup table out of the TLB and into its own file.

Translating MSR addresses into MSR register indices took a lot of space in the
TLB source and made looking around in that file awkward. This change moves
the lookup into its own file to get it out of the way. It also changes it from
a switch statement to a hash map which should hopefully be a little more
efficient.
/gem5/src/cpu/
H A Dtimebuf.hh7813:7338bc628489 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Move sched_list.hh and timebuf.hh from src/base to src/cpu.
These files really aren't general enough to belong in src/base.
This patch doesn't reorder include lines, leaving them unsorted
in many cases, but Nate's magic script will fix that up shortly.
/gem5/src/mem/slicc/ast/
H A DTypeFieldStateAST.py8086:bf0335d98250 Wed Feb 23 19:41:00 EST 2011 Brad Beckmann <Brad.Beckmann@amd.com> ruby: automate permission setting

This patch integrates permissions with cache and memory states, and then
automates the setting of permissions within the generated code. No longer
does one need to manually set the permissions within the setState funciton.
This patch will faciliate easier functional access support by always correctly
setting permissions for both cache and memory states.
/gem5/util/m5/
H A Djni_gem5Op.c8547:5979b029bbb4 Tue Sep 13 01:06:00 EDT 2011 Prakash Ramrakhyani <prakash.ramrakhyani@arm.com> gem5ops: Implement Java JNI for gem5Ops

These ops allow gem5 ops to be called from within java programs like the following:
import jni.gem5Op;

public class HelloWorld {

public static void main(String[] args) {
gem5Op gem5 = new gem5Op();
System.out.println("Rpns0:" + gem5.rpns());
System.out.println("Rpns1:" + gem5.rpns());
}

static {
System.loadLibrary("gem5OpJni");
}
}

When building you need to make sure classpath include gem5OpJni.jar:
javac -classpath $CLASSPATH:/path/to/gem5OpJni.jar HelloWorld.java

and when running you need to make sure both the java and library path are set:
java -classpath $CLASSPATH:/path/to/gem5OpJni.jar -Djava.library.path=/path/to/libgem5OpJni.so HelloWorld
/gem5/util/m5/jni/
H A Dgem5Op.java8547:5979b029bbb4 Tue Sep 13 01:06:00 EDT 2011 Prakash Ramrakhyani <prakash.ramrakhyani@arm.com> gem5ops: Implement Java JNI for gem5Ops

These ops allow gem5 ops to be called from within java programs like the following:
import jni.gem5Op;

public class HelloWorld {

public static void main(String[] args) {
gem5Op gem5 = new gem5Op();
System.out.println("Rpns0:" + gem5.rpns());
System.out.println("Rpns1:" + gem5.rpns());
}

static {
System.loadLibrary("gem5OpJni");
}
}

When building you need to make sure classpath include gem5OpJni.jar:
javac -classpath $CLASSPATH:/path/to/gem5OpJni.jar HelloWorld.java

and when running you need to make sure both the java and library path are set:
java -classpath $CLASSPATH:/path/to/gem5OpJni.jar -Djava.library.path=/path/to/libgem5OpJni.so HelloWorld
/gem5/src/arch/x86/insts/
H A Dmicrofpop.cc8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
/gem5/src/arch/sparc/
H A Dmmapped_ipr.hh8794:e2ac2b7164dd Fri Nov 18 05:20:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of includes of config/full_system.hh.
8748:01be402c5bf1 Mon Oct 10 03:31:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SPARC: Turn on handleIprRead and handleIprWrite in SE in SPARC.
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
8105:906864dd0937 Wed Mar 02 02:18:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Spelling: Fix the a spelling error by changing mmaped to mmapped.

There may not be a formally correct spelling for the past tense of mmap, but
mmapped is the spelling Google doesn't try to autocorrect. This makes sense
because it mirrors the past tense of map->mapped and not the past tense of
cape->caped.
/gem5/src/mem/ruby/network/simple/
H A DSimpleLink.hh8258:7c377f5162f8 Thu Apr 28 20:18:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com> network: basic link bw for garnet and simple networks

This patch ensures that both Garnet and the simple networks use the bw value
specified in the topology. To do so, the patch generalizes the specification
of bw for basic links. This value is then translated to the specific value
used by the simple and Garnet networks. Since Garent does not support
non-uniformed link bandwidth, the patch also adds a check to ensure all bws are
equal.
/gem5/src/mem/ruby/slicc_interface/
H A DAbstractEntry.hh8645:89929730804b Sat Dec 31 19:44:00 EST 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Shuffle some of the included files
This patch adds and removes included files from some of the files so as to
organize remove some false dependencies and include some files directly
instead of transitively.
8485:7a9a7f2a3d46 Wed Aug 03 19:25:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Remove files and includes not in use
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
8086:bf0335d98250 Wed Feb 23 19:41:00 EST 2011 Brad Beckmann <Brad.Beckmann@amd.com> ruby: automate permission setting

This patch integrates permissions with cache and memory states, and then
automates the setting of permissions within the generated code. No longer
does one need to manually set the permissions within the setState funciton.
This patch will faciliate easier functional access support by always correctly
setting permissions for both cache and memory states.
/gem5/src/arch/generic/
H A Ddebugfaults.hh8590:aafd1d2e13e3 Tue Sep 27 03:17:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Faults: Add in generic faults that work like panics, warns, etc.

These faults take varargs to their constructors which they print into a string
and pass to the M5DebugFault base class. They are basically faults wrapped
around panics, faults, warns, and warnonce-es so that they happen only at
commit.
8332:23711432221f Thu Jun 02 17:36:00 EDT 2011 Nathan Binkert <nate@binkert.org> copyright: clean up copyright blocks
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
7965:f4c89fe1246b Sun Feb 13 20:42:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> X86: Define fault objects to carry debug messages.

These faults can panic/warn/warn_once, etc., instead of instructions doing
that themselves directly. That way, instructions can be speculatively
executed, and only if they're actually going to commit will their fault be
invoked and the panic, etc., happen.
/gem5/src/base/stats/
H A Dtypes.hh8514:57c96df312a1 Fri Aug 19 16:08:00 EDT 2011 Thomas Grass <Thomas.Grass@ARM.com> Stats: Add a sparse histogram stat object.
7811:a8fc35183c10 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Make commenting on close namespace brackets consistent.

Ran all the source files through 'perl -pi' with this script:

s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|;
s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|;
s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|;

Also did a little manual editing on some of the arch/*/isa_traits.hh files
and src/SConscript.
/gem5/src/mem/ruby/profiler/
H A DAccessTraceForAddress.cc8165:5955406f7ed0 Sat Mar 19 19:34:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Convert CacheRequestType to RubyRequestType
This patch converts CacheRequestType to RubyRequestType so that both the
protocol dependent and independent code makes use of the same request type.
8164:b043c0efa024 Sat Mar 19 19:34:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Convert AccessModeType to RubyAccessMode
This patch converts AccessModeType to RubyAccessMode so that both the
protocol dependent and independent code uses the same access mode.
/gem5/src/arch/arm/isa/insts/
H A Dm5ops.isa8782:10c9297e14d5 Wed Nov 02 04:25:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in the ARM ISA.
8607:5fb918115c07 Mon Oct 31 04:09:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> GCC: Get everything working with gcc 4.6.1.

And by "everything" I mean all the quick regressions.
8555:6fd8d0432d8d Mon Sep 19 02:26:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Pseudoinst: Add an initParam pseudo inst function.
8354:26be660e365a Fri Jun 17 01:20:00 EDT 2011 Gedare Bloom <gedare@gwmail.gwu.edu> ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA.
8204:6c051a8df26a Mon Apr 04 12:42:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Fix m5op parameters bug.

All the m5op parameters are 64 bits, but we were only sending 32 bits;
and the static register indexes were incorrectly specified.
8142:e08035e1a1f6 Thu Mar 17 20:20:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Allow conditional quiesce instructions.

This patch prevents not executed conditional instructions marked as
IsQuiesce from stalling the pipeline indefinitely. If the instruction
is not executed the quiesceSkip psuedoinst is called which schedules a
wakes up call to the fetch stage.
/gem5/src/unittest/
H A Dstattest.cc8514:57c96df312a1 Fri Aug 19 16:08:00 EDT 2011 Thomas Grass <Thomas.Grass@ARM.com> Stats: Add a sparse histogram stat object.
8235:6381dc8bcfcc Fri Apr 15 13:45:00 EDT 2011 Nathan Binkert <nate@binkert.org> unittest: Make unit tests capable of using swig and python, convert stattest
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
7831:c1e158414648 Mon Jan 10 14:11:00 EST 2011 Nathan Binkert <nate@binkert.org> stats: Add a histogram statistic type
7830:8bdcec97b36b Mon Jan 10 14:11:00 EST 2011 Nathan Binkert <nate@binkert.org> stats: fix stat test from curTick change
7823:dac01f14f20f Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Replace curTick global variable with accessor functions.
This step makes it easy to replace the accessor functions
(which still access a global variable) with ones that access
per-thread curTick values.
/gem5/src/dev/arm/
H A Drv_ctrl.cc8524:1ddd1aa0e55b Fri Aug 19 16:08:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add support for Versatile Express boards
8299:64a938a8b7fc Fri May 13 18:27:00 EDT 2011 Chander Sudanthi <chander.sudanthi@arm.com> ARM: Better RealView/Versatile EB platform support.

Add registers and components to better support the VersatileEB board.
Made the MIDR and SYS_ID register parameters to ArmSystem and RealviewCtrl
respectively.
8281:a8c4b7a24d62 Wed May 04 21:38:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add support for some more registers in the real view controller.
8273:d3992e7ebc59 Wed May 04 21:38:00 EDT 2011 Chris Emmons <chris.emmons@arm.com> RealView: Fix the 24 and 100MHz clocks which were providing incorrect values.
8060:a9e16f89f11e Wed Feb 23 16:10:00 EST 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add support for read of 100MHz clock in system controller.
7950:1120b07dd4b0 Fri Feb 11 19:29:00 EST 2011 Ali Saidi <Ali.Saidi@ARM.com> VNC/ARM: Use VNC server and add support to boot into X11
7823:dac01f14f20f Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Replace curTick global variable with accessor functions.
This step makes it easy to replace the accessor functions
(which still access a global variable) with ones that access
per-thread curTick values.
/gem5/src/arch/arm/
H A Dintregs.hh8303:5a95f1d2494e Fri May 13 18:27:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Further break up condition code into NZ, C, V bits.

Break up the condition code bits into NZ, C, V registers. These are individually
written and this removes some incorrect dependencies between instructions.
8302:9f23d01421de Fri May 13 18:27:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Remove the saturating (Q) condition code from the renamed register.

Move the saturating bit (which is also saturating) from the renamed register
that holds the flags to the CPSR miscreg and adds a allows setting it in a
similar way to the FP saturating registers. This removes a dependency in
instructions that don't write, but need to preserve the Q bit.
8301:858384f3af1c Fri May 13 18:27:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Break up condition codes into normal flags, saturation, and simd.

This change splits out the condcodes from being one monolithic register
into three blocks that are updated independently. This allows CPUs
to not have to do RMW operations on the flags registers for instructions
that don't write all flags.
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
8140:7449084b1612 Thu Mar 17 20:20:00 EDT 2011 Matt Horsnell <Matt.Horsnell@arm.com> ARM: Fix RFE macrop.

This changes the RFE macroop into 3 microops:

URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack
sp = sp + offset; // optionally auto-increment
PC = URa; CPSR = URb; // write to the PC and CPSR.

Importantly:
- writing to PC is handled in the last micro-op.
- loading occurs prior to state changes.
/gem5/src/kern/
H A DSConscript8788:2d403a6d7078 Sun Nov 13 05:05:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in kern.
8777:dd43f1c9fa0a Mon Oct 31 05:58:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make the functions available from the TC consistent between SE and FS.
8774:232b5574d9c3 Sun Oct 30 20:38:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Compile in system events in SE mode.
8770:81354d3836d4 Sun Oct 30 06:06:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Build syscall_emul.cc in FS mode.
8335:9228e00459d4 Thu Jun 02 20:36:00 EDT 2011 Nathan Binkert <nate@binkert.org> scons: rename TraceFlags to DebugFlags
/gem5/src/mem/ruby/network/
H A DSConscript8492:1ad244a20877 Mon Aug 08 11:50:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> BuildEnv: Eliminate RUBY as build environment variable
This patch replaces RUBY with PROTOCOL in all the SConscript files as
the environment variable that decides whether or not certain components
of the simulator are compiled.
8257:7226aebb77b4 Thu Apr 28 20:18:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com> network: convert links & switches to first class C++ SimObjects

This patch converts links and switches from second class simobjects that were
virtually ignored by the networks (both simple and Garnet) to first class
simobjects that directly correspond to c++ ojbects manipulated by the
topology and network classes. This is especially true for Garnet, where the
links and switches directly correspond to specific C++ objects.

By making this change, many aspects of the Topology class were simplified.
8255:73089f793a0a Thu Apr 28 20:18:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com> ruby: moved topology to the top network directory

Moved the Topology class to the top network directory because it is shared by
both the simple and Garnet networks.
H A DBasicLink.py8263:8743998edfd3 Thu Apr 28 20:18:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com> network: set the ExtLink bw to 16 bytes

Therefore all links by default are 16 bytes wide and thus work with Garnet's
uniform link bandwidth assumption.
8258:7c377f5162f8 Thu Apr 28 20:18:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com> network: basic link bw for garnet and simple networks

This patch ensures that both Garnet and the simple networks use the bw value
specified in the topology. To do so, the patch generalizes the specification
of bw for basic links. This value is then translated to the specific value
used by the simple and Garnet networks. Since Garent does not support
non-uniformed link bandwidth, the patch also adds a check to ensure all bws are
equal.
8257:7226aebb77b4 Thu Apr 28 20:18:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com> network: convert links & switches to first class C++ SimObjects

This patch converts links and switches from second class simobjects that were
virtually ignored by the networks (both simple and Garnet) to first class
simobjects that directly correspond to c++ ojbects manipulated by the
topology and network classes. This is especially true for Garnet, where the
links and switches directly correspond to specific C++ objects.

By making this change, many aspects of the Topology class were simplified.

Completed in 82 milliseconds

1234567891011>>