Searched hist:2011 (Results 176 - 200 of 897) sorted by relevance
/gem5/src/sim/ | ||
H A D | stat_control.cc | 8581:56f97760eadd Thu Sep 22 21:59:00 EDT 2011 Steve Reinhardt <steve.reinhardt@amd.com> event: minor cleanup Initialize flags via the Event constructor instead of calling setFlags() in the body of the derived class's constructor. I forget exactly why, but this made life easier when implementing multi-queue support. Also rename Event::getFlags() to isFlagSet() to better match common usage, and get rid of some unused Event methods. 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes 7840:ed75cee5c793 Sat Jan 15 10:48:00 EST 2011 Nathan Binkert <nate@binkert.org> time: improve time datastructure Use posix clock functions (and librt) if it is available. Inline a bunch of functions and implement more operators. * * * time: more cleanup 7823:dac01f14f20f Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Replace curTick global variable with accessor functions. This step makes it easy to replace the accessor functions (which still access a global variable) with ones that access per-thread curTick values. 7822:fc475ac7d2a4 Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> stats: rename StatEvent() function to schedStatEvent(). This follows the style rules and is more descriptive. 7811:a8fc35183c10 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Make commenting on close namespace brackets consistent. Ran all the source files through 'perl -pi' with this script: s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|; s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|; s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|; Also did a little manual editing on some of the arch/*/isa_traits.hh files and src/SConscript. |
/gem5/src/mem/ruby/slicc_interface/ | ||
H A D | RubySlicc_Util.hh | 8608:02d7ac5fb855 Thu Nov 03 23:46:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Remove some unused typedefs This patch removes some of the unused typedefs. It also moves some of the typedefs from Global.hh to TypeDefines.hh. The patch also eliminates the file NodeID.hh. 8485:7a9a7f2a3d46 Wed Aug 03 19:25:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Remove files and includes not in use 8174:e21f6e70169e Tue Mar 22 07:41:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Remove CacheMsg class from SLICC The goal of the patch is to do away with the CacheMsg class currently in use in coherence protocols. In place of CacheMsg, the RubyRequest class will used. This class is already present in slicc_interface/RubyRequest.hh. In fact, objects of class CacheMsg are generated by copying values from a RubyRequest object. 8165:5955406f7ed0 Sat Mar 19 19:34:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Convert CacheRequestType to RubyRequestType This patch converts CacheRequestType to RubyRequestType so that both the protocol dependent and independent code makes use of the same request type. 8131:03f7df749b9d Thu Mar 17 20:01:00 EDT 2011 Lisa Hsu <Lisa.Hsu@amd.com> Ruby: expose a simple mod function in slicc interface. 7832:de7601e6e19d Mon Jan 10 14:11:00 EST 2011 Nathan Binkert <nate@binkert.org> ruby: get rid of ruby's Debug.hh Get rid of the Debug class Get rid of ASSERT and use assert Use DPRINTFR for ProtocolTrace |
/gem5/src/arch/arm/insts/ | ||
H A D | macromem.cc | 8542:7230ff0738e3 Fri Sep 09 05:40:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> StaticInst: Merge StaticInst and StaticInstBase. Having two StaticInst classes, one nominally ISA dependent and the other ISA dependent, has not been historically useful and makes the StaticInst class more complicated that it needs to be. This change merges StaticInstBase into StaticInst. 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes 8196:e46d051c35be Mon Apr 04 12:42:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Remove debugging warn that was accidently left in. 8148:93982cb5044c Thu Mar 17 20:20:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Fix subtle bug in LDM. If the instruction faults mid-op the base register shouldn't be written back. 8140:7449084b1612 Thu Mar 17 20:20:00 EDT 2011 Matt Horsnell <Matt.Horsnell@arm.com> ARM: Fix RFE macrop. This changes the RFE macroop into 3 microops: URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack sp = sp + offset; // optionally auto-increment PC = URa; CPSR = URb; // write to the PC and CPSR. Importantly: - writing to PC is handled in the last micro-op. - loading occurs prior to state changes. 7853:69aae4379062 Tue Jan 18 17:30:00 EST 2011 Matt Horsnell <Matt.Horsnell@ARM.com> ARM: The ARM decoder should not panic when decoding undefined holes is arch. This can abort simulations when the fetch unit runs ahead and speculatively decodes instructions that are off the execution path. |
/gem5/src/arch/arm/isa/insts/ | ||
H A D | str.isa | 8588:ef28ed90449d Tue Sep 27 02:48:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISA parser: Use '_' instead of '.' to delimit type modifiers on operands. By using an underscore, the "." is still available and can unambiguously be used to refer to members of a structure if an operand is a structure, class, etc. This change mostly just replaces the appropriate "."s with "_"s, but there were also a few places where the ISA descriptions where handling the extensions themselves and had their own regular expressions to update. The regular expressions in the isa parser were updated as well. It also now looks for one of the defined type extensions specifically after connecting "_" where before it would look for any sequence of characters after a "." following an operand name and try to use it as the extension. This helps to disambiguate cases where a "_" may legitimately be part of an operand name but not separate the name from the type suffix. Because leaving the "_" and suffix on the variable name still leaves a valid C++ identifier and all extensions need to be consistent in a given context, I considered leaving them on as a breadcrumb that would show what the intended type was for that operand. Unfortunately the operands can be referred to in code templates, the Mem operand in particular, and since the exact type of Mem can be different for different uses of the same template, that broke things. 8304:16911ff780d3 Fri May 13 18:27:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Construct the predicate test register for more instruction programatically. If one of the condition codes isn't being used in the execution we should only read it if the instruction might be dependent on it. With the preeceding changes there are several more cases where we should dynamically pick instead of assuming as we did before. 8303:5a95f1d2494e Fri May 13 18:27:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Further break up condition code into NZ, C, V bits. Break up the condition code bits into NZ, C, V registers. These are individually written and this removes some incorrect dependencies between instructions. 8301:858384f3af1c Fri May 13 18:27:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Break up condition codes into normal flags, saturation, and simd. This change splits out the condcodes from being one monolithic register into three blocks that are updated independently. This allows CPUs to not have to do RMW operations on the flags registers for instructions that don't write all flags. 8136:afcb66f4b964 Thu Mar 17 20:20:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Previous change didn't end up setting instFlags, this does. 8069:a3f5f75db279 Wed Feb 23 16:10:00 EST 2011 Matt Horsnell <Matt.Horsnell@arm.com> ARM: Mark store conditionals as such. |
H A D | macromem.isa | 8607:5fb918115c07 Mon Oct 31 04:09:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> GCC: Get everything working with gcc 4.6.1. And by "everything" I mean all the quick regressions. 8588:ef28ed90449d Tue Sep 27 02:48:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISA parser: Use '_' instead of '.' to delimit type modifiers on operands. By using an underscore, the "." is still available and can unambiguously be used to refer to members of a structure if an operand is a structure, class, etc. This change mostly just replaces the appropriate "."s with "_"s, but there were also a few places where the ISA descriptions where handling the extensions themselves and had their own regular expressions to update. The regular expressions in the isa parser were updated as well. It also now looks for one of the defined type extensions specifically after connecting "_" where before it would look for any sequence of characters after a "." following an operand name and try to use it as the extension. This helps to disambiguate cases where a "_" may legitimately be part of an operand name but not separate the name from the type suffix. Because leaving the "_" and suffix on the variable name still leaves a valid C++ identifier and all extensions need to be consistent in a given context, I considered leaving them on as a breadcrumb that would show what the intended type was for that operand. Unfortunately the operands can be referred to in code templates, the Mem operand in particular, and since the exact type of Mem can be different for different uses of the same template, that broke things. 8309:d1ce92fd3245 Wed May 18 14:06:00 EDT 2011 Nathan Binkert <nate@binkert.org> gcc: fix an uninitialized variable warning from G++ 4.5 8304:16911ff780d3 Fri May 13 18:27:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Construct the predicate test register for more instruction programatically. If one of the condition codes isn't being used in the execution we should only read it if the instruction might be dependent on it. With the preeceding changes there are several more cases where we should dynamically pick instead of assuming as we did before. 8303:5a95f1d2494e Fri May 13 18:27:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Further break up condition code into NZ, C, V bits. Break up the condition code bits into NZ, C, V registers. These are individually written and this removes some incorrect dependencies between instructions. 8302:9f23d01421de Fri May 13 18:27:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Remove the saturating (Q) condition code from the renamed register. Move the saturating bit (which is also saturating) from the renamed register that holds the flags to the CPSR miscreg and adds a allows setting it in a similar way to the FP saturating registers. This removes a dependency in instructions that don't write, but need to preserve the Q bit. 8301:858384f3af1c Fri May 13 18:27:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Break up condition codes into normal flags, saturation, and simd. This change splits out the condcodes from being one monolithic register into three blocks that are updated independently. This allows CPUs to not have to do RMW operations on the flags registers for instructions that don't write all flags. 8285:c38905a6fa32 Wed May 04 21:38:00 EDT 2011 Prakash Ramrakhyani <Prakash.Ramrakhyani@arm.com> ARM: Implement WFE/WFI/SEV semantics. 8205:7ecbffb674aa Mon Apr 04 12:42:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Cleanup implementation of ITSTATE and put important code in PCState. Consolidate all code to handle ITSTATE in the PCState object rather than touching a variety of structures/objects. 8148:93982cb5044c Thu Mar 17 20:20:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Fix subtle bug in LDM. If the instruction faults mid-op the base register shouldn't be written back. |
H A D | ldr.isa | 8588:ef28ed90449d Tue Sep 27 02:48:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISA parser: Use '_' instead of '.' to delimit type modifiers on operands. By using an underscore, the "." is still available and can unambiguously be used to refer to members of a structure if an operand is a structure, class, etc. This change mostly just replaces the appropriate "."s with "_"s, but there were also a few places where the ISA descriptions where handling the extensions themselves and had their own regular expressions to update. The regular expressions in the isa parser were updated as well. It also now looks for one of the defined type extensions specifically after connecting "_" where before it would look for any sequence of characters after a "." following an operand name and try to use it as the extension. This helps to disambiguate cases where a "_" may legitimately be part of an operand name but not separate the name from the type suffix. Because leaving the "_" and suffix on the variable name still leaves a valid C++ identifier and all extensions need to be consistent in a given context, I considered leaving them on as a breadcrumb that would show what the intended type was for that operand. Unfortunately the operands can be referred to in code templates, the Mem operand in particular, and since the exact type of Mem can be different for different uses of the same template, that broke things. 8304:16911ff780d3 Fri May 13 18:27:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Construct the predicate test register for more instruction programatically. If one of the condition codes isn't being used in the execution we should only read it if the instruction might be dependent on it. With the preeceding changes there are several more cases where we should dynamically pick instead of assuming as we did before. 8303:5a95f1d2494e Fri May 13 18:27:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Further break up condition code into NZ, C, V bits. Break up the condition code bits into NZ, C, V registers. These are individually written and this removes some incorrect dependencies between instructions. 8302:9f23d01421de Fri May 13 18:27:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Remove the saturating (Q) condition code from the renamed register. Move the saturating bit (which is also saturating) from the renamed register that holds the flags to the CPSR miscreg and adds a allows setting it in a similar way to the FP saturating registers. This removes a dependency in instructions that don't write, but need to preserve the Q bit. 8301:858384f3af1c Fri May 13 18:27:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Break up condition codes into normal flags, saturation, and simd. This change splits out the condcodes from being one monolithic register into three blocks that are updated independently. This allows CPUs to not have to do RMW operations on the flags registers for instructions that don't write all flags. 8203:78b9f056d58a Mon Apr 04 12:42:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Tag appropriate instructions as IsReturn 8140:7449084b1612 Thu Mar 17 20:20:00 EDT 2011 Matt Horsnell <Matt.Horsnell@arm.com> ARM: Fix RFE macrop. This changes the RFE macroop into 3 microops: URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack sp = sp + offset; // optionally auto-increment PC = URa; CPSR = URb; // write to the PC and CPSR. Importantly: - writing to PC is handled in the last micro-op. - loading occurs prior to state changes. 7858:ee6641d7c713 Tue Jan 18 17:30:00 EST 2011 Matt.Horsnell <Matt.Horsnell@arm.com> O3: Fix itstate prediction and recovery. Any change of control flow now resets the itstate to 0 mask and 0 condition, except where the control flow alteration write into the cpsr register. These case, for example return from an iterrupt, require the predecoder to recover the itstate. As there is a window of opportunity between the return from an interrupt changing the control flow at the head of the pipe and the commit of the update to the CPSR, the predecoder needs to be able to grab the ITstate early. This is now handled by setting the forcedItState inside a PCstate for the control flow altering instruction. That instruction will have the correct mask/cond, but will not have a valid itstate until advancePC is called (note this happens to advance the execution). When the new PCstate is copy constructed it gets the itstate cond/mask, and upon advancing the PC the itstate becomes valid. Subsequent advancing invalidates the state and zeroes the cond/mask. This is handled in isolation for the ARM ISA and should have no impact on other ISAs. Refer arch/arm/types.hh and arch/arm/predecoder.cc for the details. |
/gem5/src/mem/slicc/ast/ | ||
H A D | IsValidPtrExprAST.py | 8192:be38f7b6ad9e Thu Mar 31 20:18:00 EDT 2011 Lisa Hsu <Lisa.Hsu@amd.com> Ruby: Simplify SLICC and Entry/TBE handling. Before this changeset, all local variables of type Entry and TBE were considered to be pointers, but an immediate use of said variables would not be automatically deferenced in SLICC-generated code. Instead, deferences occurred when such variables were passed to functions, and were automatically dereferenced in the bodies of the functions (e.g. the implicitly passed cache_entry). This is a more general way to do it, which leaves in place the assumption that parameters to functions and local variables of type AbstractCacheEntry and TBE are always pointers, but instead of dereferencing to access member variables on a contextual basis, the dereferencing automatically occurs on a type basis at the moment a member is being accessed. So, now, things you can do that you couldn't before include: Entry foo := getCacheEntry(address); cache_entry.DataBlk := foo.DataBlk; or cache_entry.DataBlk := getCacheEntry(address).DataBlk; or even cache_entry.DataBlk := static_cast(Entry, pointer, cache.lookup(address)).DataBlk; 7839:9e556fb25900 Mon Jan 17 19:46:00 EST 2011 Nilay Vaish<nilay@cs.wisc.edu> Change interface between coherence protocols and CacheMemory The purpose of this patch is to change the way CacheMemory interfaces with coherence protocols. Currently, whenever a cache controller (defined in the protocol under consideration) needs to carry out any operation on a cache block, it looks up the tag hash map and figures out whether or not the block exists in the cache. In case it does exist, the operation is carried out (which requires another lookup). As observed through profiling of different protocols, multiple such lookups take place for a given cache block. It was noted that the tag lookup takes anything from 10% to 20% of the simulation time. In order to reduce this time, this patch is being posted. I have to acknowledge that the many of the thoughts that went in to this patch belong to Brad. Changes to CacheMemory, TBETable and AbstractCacheEntry classes: 1. The lookup function belonging to CacheMemory class now returns a pointer to a cache block entry, instead of a reference. The pointer is NULL in case the block being looked up is not present in the cache. Similar change has been carried out in the lookup function of the TBETable class. 2. Function for setting and getting access permission of a cache block have been moved from CacheMemory class to AbstractCacheEntry class. 3. The allocate function in CacheMemory class now returns pointer to the allocated cache entry. Changes to SLICC: 1. Each action now has implicit variables - cache_entry and tbe. cache_entry, if != NULL, must point to the cache entry for the address on which the action is being carried out. Similarly, tbe should also point to the transaction buffer entry of the address on which the action is being carried out. 2. If a cache entry or a transaction buffer entry is passed on as an argument to a function, it is presumed that a pointer is being passed on. 3. The cache entry and the tbe pointers received __implicitly__ by the actions, are passed __explicitly__ to the trigger function. 4. While performing an action, set/unset_cache_entry, set/unset_tbe are to be used for setting / unsetting cache entry and tbe pointers respectively. 5. is_valid() and is_invalid() has been made available for testing whether a given pointer 'is not NULL' and 'is NULL' respectively. 6. Local variables are now available, but they are assumed to be pointers always. 7. It is now possible for an object of the derieved class to make calls to a function defined in the interface. 8. An OOD token has been introduced in SLICC. It is same as the NULL token used in C/C++. If you are wondering, OOD stands for Out Of Domain. 9. static_cast can now taken an optional parameter that asks for casting the given variable to a pointer of the given type. 10. Functions can be annotated with 'return_by_pointer=yes' to return a pointer. 11. StateMachine has two new variables, EntryType and TBEType. EntryType is set to the type which inherits from 'AbstractCacheEntry'. There can only be one such type in the machine. TBEType is set to the type for which 'TBE' is used as the name. All the protocols have been modified to conform with the new interface. |
H A D | ActionDeclAST.py | 8192:be38f7b6ad9e Thu Mar 31 20:18:00 EDT 2011 Lisa Hsu <Lisa.Hsu@amd.com> Ruby: Simplify SLICC and Entry/TBE handling. Before this changeset, all local variables of type Entry and TBE were considered to be pointers, but an immediate use of said variables would not be automatically deferenced in SLICC-generated code. Instead, deferences occurred when such variables were passed to functions, and were automatically dereferenced in the bodies of the functions (e.g. the implicitly passed cache_entry). This is a more general way to do it, which leaves in place the assumption that parameters to functions and local variables of type AbstractCacheEntry and TBE are always pointers, but instead of dereferencing to access member variables on a contextual basis, the dereferencing automatically occurs on a type basis at the moment a member is being accessed. So, now, things you can do that you couldn't before include: Entry foo := getCacheEntry(address); cache_entry.DataBlk := foo.DataBlk; or cache_entry.DataBlk := getCacheEntry(address).DataBlk; or even cache_entry.DataBlk := static_cast(Entry, pointer, cache.lookup(address)).DataBlk; 7839:9e556fb25900 Mon Jan 17 19:46:00 EST 2011 Nilay Vaish<nilay@cs.wisc.edu> Change interface between coherence protocols and CacheMemory The purpose of this patch is to change the way CacheMemory interfaces with coherence protocols. Currently, whenever a cache controller (defined in the protocol under consideration) needs to carry out any operation on a cache block, it looks up the tag hash map and figures out whether or not the block exists in the cache. In case it does exist, the operation is carried out (which requires another lookup). As observed through profiling of different protocols, multiple such lookups take place for a given cache block. It was noted that the tag lookup takes anything from 10% to 20% of the simulation time. In order to reduce this time, this patch is being posted. I have to acknowledge that the many of the thoughts that went in to this patch belong to Brad. Changes to CacheMemory, TBETable and AbstractCacheEntry classes: 1. The lookup function belonging to CacheMemory class now returns a pointer to a cache block entry, instead of a reference. The pointer is NULL in case the block being looked up is not present in the cache. Similar change has been carried out in the lookup function of the TBETable class. 2. Function for setting and getting access permission of a cache block have been moved from CacheMemory class to AbstractCacheEntry class. 3. The allocate function in CacheMemory class now returns pointer to the allocated cache entry. Changes to SLICC: 1. Each action now has implicit variables - cache_entry and tbe. cache_entry, if != NULL, must point to the cache entry for the address on which the action is being carried out. Similarly, tbe should also point to the transaction buffer entry of the address on which the action is being carried out. 2. If a cache entry or a transaction buffer entry is passed on as an argument to a function, it is presumed that a pointer is being passed on. 3. The cache entry and the tbe pointers received __implicitly__ by the actions, are passed __explicitly__ to the trigger function. 4. While performing an action, set/unset_cache_entry, set/unset_tbe are to be used for setting / unsetting cache entry and tbe pointers respectively. 5. is_valid() and is_invalid() has been made available for testing whether a given pointer 'is not NULL' and 'is NULL' respectively. 6. Local variables are now available, but they are assumed to be pointers always. 7. It is now possible for an object of the derieved class to make calls to a function defined in the interface. 8. An OOD token has been introduced in SLICC. It is same as the NULL token used in C/C++. If you are wondering, OOD stands for Out Of Domain. 9. static_cast can now taken an optional parameter that asks for casting the given variable to a pointer of the given type. 10. Functions can be annotated with 'return_by_pointer=yes' to return a pointer. 11. StateMachine has two new variables, EntryType and TBEType. EntryType is set to the type which inherits from 'AbstractCacheEntry'. There can only be one such type in the machine. TBEType is set to the type for which 'TBE' is used as the name. All the protocols have been modified to conform with the new interface. |
/gem5/src/dev/alpha/ | ||
H A D | backdoor.hh | 8789:a8b63a0ee14c Sun Nov 13 05:05:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in dev. 8739:925f15f96322 Fri Sep 30 03:28:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Build the devices in SE mode. |
/gem5/src/dev/arm/ | ||
H A D | amba_device.hh | 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes 7950:1120b07dd4b0 Fri Feb 11 19:29:00 EST 2011 Ali Saidi <Ali.Saidi@ARM.com> VNC/ARM: Use VNC server and add support to boot into X11 |
/gem5/src/dev/x86/ | ||
H A D | i8237.hh | 7903:7fcfb515d7bf Mon Feb 07 01:14:00 EST 2011 Joel Hestness <hestness@cs.utexas.edu> x86: Add checkpointing capability to devices Add checkpointing capability to the Intel 8254 timer, CMOS, I8042, PS2 Keyboard and Mouse, I82094AA, I8237, I8254, I8259, and speaker devices 7811:a8fc35183c10 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Make commenting on close namespace brackets consistent. Ran all the source files through 'perl -pi' with this script: s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|; s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|; s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|; Also did a little manual editing on some of the arch/*/isa_traits.hh files and src/SConscript. |
H A D | speaker.hh | 7903:7fcfb515d7bf Mon Feb 07 01:14:00 EST 2011 Joel Hestness <hestness@cs.utexas.edu> x86: Add checkpointing capability to devices Add checkpointing capability to the Intel 8254 timer, CMOS, I8042, PS2 Keyboard and Mouse, I82094AA, I8237, I8254, I8259, and speaker devices 7811:a8fc35183c10 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Make commenting on close namespace brackets consistent. Ran all the source files through 'perl -pi' with this script: s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|; s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|; s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|; Also did a little manual editing on some of the arch/*/isa_traits.hh files and src/SConscript. |
H A D | speaker.cc | 8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help 7903:7fcfb515d7bf Mon Feb 07 01:14:00 EST 2011 Joel Hestness <hestness@cs.utexas.edu> x86: Add checkpointing capability to devices Add checkpointing capability to the Intel 8254 timer, CMOS, I8042, PS2 Keyboard and Mouse, I82094AA, I8237, I8254, I8259, and speaker devices |
H A D | i8254.cc | 8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help 7903:7fcfb515d7bf Mon Feb 07 01:14:00 EST 2011 Joel Hestness <hestness@cs.utexas.edu> x86: Add checkpointing capability to devices Add checkpointing capability to the Intel 8254 timer, CMOS, I8042, PS2 Keyboard and Mouse, I82094AA, I8237, I8254, I8259, and speaker devices |
H A D | SConscript | 8739:925f15f96322 Fri Sep 30 03:28:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Build the devices in SE mode. 8335:9228e00459d4 Thu Jun 02 20:36:00 EDT 2011 Nathan Binkert <nate@binkert.org> scons: rename TraceFlags to DebugFlags |
/gem5/src/base/ | ||
H A D | cp_annotate.hh | 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes 7823:dac01f14f20f Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Replace curTick global variable with accessor functions. This step makes it easy to replace the accessor functions (which still access a global variable) with ones that access per-thread curTick values. |
H A D | cp_annotate.cc | 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes 7823:dac01f14f20f Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Replace curTick global variable with accessor functions. This step makes it easy to replace the accessor functions (which still access a global variable) with ones that access per-thread curTick values. |
/gem5/src/arch/mips/ | ||
H A D | system.cc | 8775:1e3ca5d77b53 Sun Oct 30 21:39:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in MIPS. 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes |
/gem5/src/cpu/ | ||
H A D | nativetrace.cc | 8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help 7811:a8fc35183c10 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Make commenting on close namespace brackets consistent. Ran all the source files through 'perl -pi' with this script: s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|; s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|; s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|; Also did a little manual editing on some of the arch/*/isa_traits.hh files and src/SConscript. |
/gem5/src/mem/ruby/network/simple/ | ||
H A D | Throttle.cc | 8645:89929730804b Sat Dec 31 19:44:00 EST 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Shuffle some of the included files This patch adds and removes included files from some of the files so as to organize remove some false dependencies and include some files directly instead of transitively. 8608:02d7ac5fb855 Thu Nov 03 23:46:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Remove some unused typedefs This patch removes some of the unused typedefs. It also moves some of the typedefs from Global.hh to TypeDefines.hh. The patch also eliminates the file NodeID.hh. 8485:7a9a7f2a3d46 Wed Aug 03 19:25:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Remove files and includes not in use 8259:36987780169e Thu Apr 28 20:18:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com> network: moved network config params Moved the buffer_size, endpoint_bandwidth, and adaptive_routing params out of the top-level parent network object and to only those networks that actually use those parameters. 8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes 8054:9138d38eccd7 Wed Feb 23 00:58:00 EST 2011 Korey Sewell <ksewell@umich.edu> ruby: cleaning up RubyQueue and RubyNetwork dprintfs Overall, continue to progress Ruby debug messages to more of the normal M5 debug message style - add a name() to the Ruby Throttle & PerfectSwitch objects so that the debug output isn't littered w/"global:" everywhere. - clean up messages that print over multiple lines when possible - clean up duplicate prints in the message buffer 7832:de7601e6e19d Mon Jan 10 14:11:00 EST 2011 Nathan Binkert <nate@binkert.org> ruby: get rid of ruby's Debug.hh Get rid of the Debug class Get rid of ASSERT and use assert Use DPRINTFR for ProtocolTrace |
/gem5/src/cpu/testers/rubytest/ | ||
H A D | CheckTable.cc | 8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes |
/gem5/src/arch/arm/linux/ | ||
H A D | process.hh | 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes 8216:70e61aa65759 Sun Apr 10 21:02:00 EDT 2011 Ali Saidi <saidi@eecs.umich.edu> ARM: Fix checkpoint restoration in ARM_SE. |
/gem5/src/kern/solaris/ | ||
H A D | solaris.hh | 8794:e2ac2b7164dd Fri Nov 18 05:20:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of includes of config/full_system.hh. 8776:17efd86a39d3 Sun Oct 30 21:52:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Build the solaris object in both SE and FS. |
/gem5/util/m5/ | ||
H A D | m5op_arm.S | 8355:89071b71691e Fri Jun 17 01:20:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Cleanup m5ops usage of r0 and r1 a bit. 8354:26be660e365a Fri Jun 17 01:20:00 EDT 2011 Gedare Bloom <gedare@gwmail.gwu.edu> ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA. |
/gem5/src/python/m5/ | ||
H A D | debug.py | 8269:5a9a639ce16f Wed May 04 10:08:00 EDT 2011 Nathan Binkert <nate@binkert.org> debug: fix help output 8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help |
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