17119SN/A// -*- mode:c++ -*- 27119SN/A 313589Sgiacomo.travaglini@arm.com// Copyright (c) 2010-2011,2017,2019 ARM Limited 47119SN/A// All rights reserved 57119SN/A// 67119SN/A// The license below extends only to copyright in the software and shall 77119SN/A// not be construed as granting a license to any other intellectual 87119SN/A// property including but not limited to intellectual property relating 97119SN/A// to a hardware implementation of the functionality of the software 107119SN/A// licensed hereunder. You may use the software subject to the license 117119SN/A// terms below provided that you ensure that this notice is replicated 127119SN/A// unmodified and in its entirety in all distributions of the software, 137119SN/A// modified or unmodified, in source code or in binary form. 147119SN/A// 157119SN/A// Redistribution and use in source and binary forms, with or without 167119SN/A// modification, are permitted provided that the following conditions are 177119SN/A// met: redistributions of source code must retain the above copyright 187119SN/A// notice, this list of conditions and the following disclaimer; 197119SN/A// redistributions in binary form must reproduce the above copyright 207119SN/A// notice, this list of conditions and the following disclaimer in the 217119SN/A// documentation and/or other materials provided with the distribution; 227119SN/A// neither the name of the copyright holders nor the names of its 237119SN/A// contributors may be used to endorse or promote products derived from 247119SN/A// this software without specific prior written permission. 257119SN/A// 267119SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277119SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287119SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297119SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307119SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317119SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327119SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337119SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347119SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357119SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367119SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377119SN/A// 387119SN/A// Authors: Gabe Black 397119SN/A 407119SN/Alet {{ 4110037SARM gem5 Developers import math 427119SN/A 437119SN/A header_output = "" 447119SN/A decoder_output = "" 457119SN/A exec_output = "" 467119SN/A 477590Sgblack@eecs.umich.edu class StoreInst(LoadStoreInst): 487590Sgblack@eecs.umich.edu execBase = 'Store' 497119SN/A 507590Sgblack@eecs.umich.edu def __init__(self, mnem, post, add, writeback, size=4, 5113588Sgiacomo.travaglini@arm.com sign=False, user=False, flavor="normal"): 527590Sgblack@eecs.umich.edu super(StoreInst, self).__init__() 537590Sgblack@eecs.umich.edu 547590Sgblack@eecs.umich.edu self.name = mnem 557590Sgblack@eecs.umich.edu self.post = post 567590Sgblack@eecs.umich.edu self.add = add 577590Sgblack@eecs.umich.edu self.writeback = writeback 587590Sgblack@eecs.umich.edu self.size = size 597590Sgblack@eecs.umich.edu self.sign = sign 607590Sgblack@eecs.umich.edu self.user = user 617590Sgblack@eecs.umich.edu self.flavor = flavor 6213588Sgiacomo.travaglini@arm.com self.instFlags = [] 637590Sgblack@eecs.umich.edu if self.add: 647590Sgblack@eecs.umich.edu self.op = " +" 657590Sgblack@eecs.umich.edu else: 667590Sgblack@eecs.umich.edu self.op = " -" 677590Sgblack@eecs.umich.edu 687590Sgblack@eecs.umich.edu self.memFlags = ["ArmISA::TLB::MustBeOne"] 697590Sgblack@eecs.umich.edu self.codeBlobs = { "postacc_code" : "" } 707590Sgblack@eecs.umich.edu 717646Sgene.wu@arm.com def emitHelper(self, base = 'Memory', wbDecl = None): 727590Sgblack@eecs.umich.edu 737590Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 747590Sgblack@eecs.umich.edu 757590Sgblack@eecs.umich.edu codeBlobs = self.codeBlobs 767590Sgblack@eecs.umich.edu codeBlobs["predicate_test"] = pickPredicate(codeBlobs) 777590Sgblack@eecs.umich.edu (newHeader, 787590Sgblack@eecs.umich.edu newDecoder, 797590Sgblack@eecs.umich.edu newExec) = self.fillTemplates(self.name, self.Name, codeBlobs, 8010037SARM gem5 Developers self.memFlags, self.instFlags, 8110037SARM gem5 Developers base, wbDecl, None, False, 8210037SARM gem5 Developers self.size, self.sign) 837590Sgblack@eecs.umich.edu 847590Sgblack@eecs.umich.edu header_output += newHeader 857590Sgblack@eecs.umich.edu decoder_output += newDecoder 867590Sgblack@eecs.umich.edu exec_output += newExec 877590Sgblack@eecs.umich.edu 887590Sgblack@eecs.umich.edu class SrsInst(LoadStoreInst): 897590Sgblack@eecs.umich.edu execBase = 'Store' 907590Sgblack@eecs.umich.edu decConstBase = 'Srs' 917590Sgblack@eecs.umich.edu 927590Sgblack@eecs.umich.edu def __init__(self, mnem, post, add, writeback): 937590Sgblack@eecs.umich.edu super(SrsInst, self).__init__() 947590Sgblack@eecs.umich.edu self.name = mnem 957590Sgblack@eecs.umich.edu self.post = post 967590Sgblack@eecs.umich.edu self.add = add 977590Sgblack@eecs.umich.edu self.writeback = writeback 987590Sgblack@eecs.umich.edu 997590Sgblack@eecs.umich.edu self.Name = "SRS_" + storeImmClassName(post, add, writeback, 8) 1007590Sgblack@eecs.umich.edu 1017590Sgblack@eecs.umich.edu def emit(self): 1027590Sgblack@eecs.umich.edu offset = 0 1037590Sgblack@eecs.umich.edu if self.post != self.add: 1047590Sgblack@eecs.umich.edu offset += 4 1057590Sgblack@eecs.umich.edu if not self.add: 1067590Sgblack@eecs.umich.edu offset -= 8 1077590Sgblack@eecs.umich.edu 1087590Sgblack@eecs.umich.edu eaCode = "EA = SpMode + %d;" % offset 1097590Sgblack@eecs.umich.edu 1107590Sgblack@eecs.umich.edu wbDiff = -8 1117590Sgblack@eecs.umich.edu if self.add: 1127590Sgblack@eecs.umich.edu wbDiff = 8 1137590Sgblack@eecs.umich.edu accCode = ''' 11412788Sgiacomo.travaglini@arm.com 11512788Sgiacomo.travaglini@arm.com auto tc = xc->tcBase(); 11612788Sgiacomo.travaglini@arm.com if (badMode32(tc, static_cast<OperatingMode>(regMode))) { 11714172Sgiacomo.travaglini@arm.com return undefinedFault32(tc, currEL(tc)); 11812788Sgiacomo.travaglini@arm.com } 11912788Sgiacomo.travaglini@arm.com 1207590Sgblack@eecs.umich.edu CPSR cpsr = Cpsr; 1218588Sgblack@eecs.umich.edu Mem_ud = (uint64_t)cSwap(LR_uw, cpsr.e) | 1228588Sgblack@eecs.umich.edu ((uint64_t)cSwap(Spsr_uw, cpsr.e) << 32); 1237590Sgblack@eecs.umich.edu ''' 1247590Sgblack@eecs.umich.edu 1257590Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 1267590Sgblack@eecs.umich.edu 1277590Sgblack@eecs.umich.edu codeBlobs = { "ea_code": eaCode, 1287590Sgblack@eecs.umich.edu "memacc_code": accCode, 1297590Sgblack@eecs.umich.edu "postacc_code": "" } 1307590Sgblack@eecs.umich.edu codeBlobs["predicate_test"] = pickPredicate(codeBlobs) 1317590Sgblack@eecs.umich.edu 1327746SAli.Saidi@ARM.com wbDecl = None 1337746SAli.Saidi@ARM.com if self.writeback: 1347746SAli.Saidi@ARM.com wbDecl = '''MicroAddiUop(machInst, 1357746SAli.Saidi@ARM.com intRegInMode((OperatingMode)regMode, INTREG_SP), 1367746SAli.Saidi@ARM.com intRegInMode((OperatingMode)regMode, INTREG_SP), 1377746SAli.Saidi@ARM.com %d);''' % wbDiff 1387746SAli.Saidi@ARM.com 1397590Sgblack@eecs.umich.edu (newHeader, 1407590Sgblack@eecs.umich.edu newDecoder, 1417590Sgblack@eecs.umich.edu newExec) = self.fillTemplates(self.name, self.Name, codeBlobs, 1427590Sgblack@eecs.umich.edu ["ArmISA::TLB::AlignWord", "ArmISA::TLB::MustBeOne"], [], 1437746SAli.Saidi@ARM.com 'SrsOp', wbDecl) 1447590Sgblack@eecs.umich.edu 1457590Sgblack@eecs.umich.edu header_output += newHeader 1467590Sgblack@eecs.umich.edu decoder_output += newDecoder 1477590Sgblack@eecs.umich.edu exec_output += newExec 1487590Sgblack@eecs.umich.edu 1497590Sgblack@eecs.umich.edu class StoreImmInst(StoreInst): 1507590Sgblack@eecs.umich.edu def __init__(self, *args, **kargs): 1517590Sgblack@eecs.umich.edu super(StoreImmInst, self).__init__(*args, **kargs) 1527590Sgblack@eecs.umich.edu self.offset = self.op + " imm" 1537590Sgblack@eecs.umich.edu 1547646Sgene.wu@arm.com if self.add: 1557646Sgene.wu@arm.com self.wbDecl = "MicroAddiUop(machInst, base, base, imm);" 1567646Sgene.wu@arm.com else: 1577646Sgene.wu@arm.com self.wbDecl = "MicroSubiUop(machInst, base, base, imm);" 1587646Sgene.wu@arm.com 1597590Sgblack@eecs.umich.edu class StoreRegInst(StoreInst): 1607590Sgblack@eecs.umich.edu def __init__(self, *args, **kargs): 1617590Sgblack@eecs.umich.edu super(StoreRegInst, self).__init__(*args, **kargs) 1627590Sgblack@eecs.umich.edu self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \ 1638304SAli.Saidi@ARM.com " shiftType, OptShiftRmCondCodesC)" 1647646Sgene.wu@arm.com if self.add: 1657646Sgene.wu@arm.com self.wbDecl = ''' 1667646Sgene.wu@arm.com MicroAddUop(machInst, base, base, index, shiftAmt, shiftType); 1677646Sgene.wu@arm.com ''' 1687646Sgene.wu@arm.com else: 1697646Sgene.wu@arm.com self.wbDecl = ''' 1707646Sgene.wu@arm.com MicroSubUop(machInst, base, base, index, shiftAmt, shiftType); 1717646Sgene.wu@arm.com ''' 1727590Sgblack@eecs.umich.edu 1737590Sgblack@eecs.umich.edu class StoreSingle(StoreInst): 1747590Sgblack@eecs.umich.edu def __init__(self, *args, **kargs): 1757590Sgblack@eecs.umich.edu super(StoreSingle, self).__init__(*args, **kargs) 1767590Sgblack@eecs.umich.edu 1777590Sgblack@eecs.umich.edu # Build the default class name 1787590Sgblack@eecs.umich.edu self.Name = self.nameFunc(self.post, self.add, self.writeback, 1797590Sgblack@eecs.umich.edu self.size, self.sign, self.user) 1807590Sgblack@eecs.umich.edu 1817590Sgblack@eecs.umich.edu # Add memory request flags where necessary 18210037SARM gem5 Developers self.memFlags.append("%d" % int(math.log(self.size, 2))) 1837590Sgblack@eecs.umich.edu if self.user: 1847590Sgblack@eecs.umich.edu self.memFlags.append("ArmISA::TLB::UserMode") 1857590Sgblack@eecs.umich.edu 18613589Sgiacomo.travaglini@arm.com if self.flavor in ("exclusive", "relex"): 18713588Sgiacomo.travaglini@arm.com self.instFlags.append("IsStoreConditional") 1887590Sgblack@eecs.umich.edu self.memFlags.append("Request::LLSC") 1897590Sgblack@eecs.umich.edu elif self.flavor != "fp": 1907590Sgblack@eecs.umich.edu self.memFlags.append("ArmISA::TLB::AllowUnaligned") 1917590Sgblack@eecs.umich.edu 19213589Sgiacomo.travaglini@arm.com if self.flavor in ("release", "relex"): 19313589Sgiacomo.travaglini@arm.com self.instFlags.extend(["IsMemBarrier", 19413589Sgiacomo.travaglini@arm.com "IsWriteBarrier", 19513589Sgiacomo.travaglini@arm.com "IsReadBarrier"]) 19613589Sgiacomo.travaglini@arm.com 1977590Sgblack@eecs.umich.edu # Disambiguate the class name for different flavors of stores 1987590Sgblack@eecs.umich.edu if self.flavor != "normal": 1997590Sgblack@eecs.umich.edu self.Name = "%s_%s" % (self.name.upper(), self.Name) 2007590Sgblack@eecs.umich.edu 2017590Sgblack@eecs.umich.edu def emit(self): 2027590Sgblack@eecs.umich.edu # Address computation 2037590Sgblack@eecs.umich.edu eaCode = "EA = Base" 2047590Sgblack@eecs.umich.edu if not self.post: 2057590Sgblack@eecs.umich.edu eaCode += self.offset 2067590Sgblack@eecs.umich.edu eaCode += ";" 2077644Sali.saidi@arm.com 2087644Sali.saidi@arm.com if self.flavor == "fp": 2097644Sali.saidi@arm.com eaCode += vfpEnabledCheckCode 2107644Sali.saidi@arm.com 2117590Sgblack@eecs.umich.edu self.codeBlobs["ea_code"] = eaCode 2127590Sgblack@eecs.umich.edu 2137590Sgblack@eecs.umich.edu # Code that actually handles the access 2147590Sgblack@eecs.umich.edu if self.flavor == "fp": 2158588Sgblack@eecs.umich.edu accCode = 'Mem%(suffix)s = cSwap(FpDest_uw, ((CPSR)Cpsr).e);' 2167590Sgblack@eecs.umich.edu else: 2177590Sgblack@eecs.umich.edu accCode = \ 2187590Sgblack@eecs.umich.edu 'Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);' 2197590Sgblack@eecs.umich.edu accCode = accCode % \ 2207590Sgblack@eecs.umich.edu { "suffix" : buildMemSuffix(self.sign, self.size) } 2217590Sgblack@eecs.umich.edu 2227590Sgblack@eecs.umich.edu self.codeBlobs["memacc_code"] = accCode 2237590Sgblack@eecs.umich.edu 2247590Sgblack@eecs.umich.edu # Push it out to the output files 2257590Sgblack@eecs.umich.edu base = buildMemBase(self.basePrefix, self.post, self.writeback) 2267646Sgene.wu@arm.com wbDecl = None 2277646Sgene.wu@arm.com if self.writeback: 2287646Sgene.wu@arm.com wbDecl = self.wbDecl 2297646Sgene.wu@arm.com self.emitHelper(base, wbDecl) 2307590Sgblack@eecs.umich.edu 2317590Sgblack@eecs.umich.edu def storeImmClassName(post, add, writeback, size=4, sign=False, user=False): 2327590Sgblack@eecs.umich.edu return memClassName("STORE_IMM", post, add, writeback, size, sign, user) 2337590Sgblack@eecs.umich.edu 2347590Sgblack@eecs.umich.edu class StoreImmEx(StoreImmInst, StoreSingle): 2357590Sgblack@eecs.umich.edu execBase = 'StoreEx' 2367590Sgblack@eecs.umich.edu decConstBase = 'StoreExImm' 2377590Sgblack@eecs.umich.edu basePrefix = 'MemoryExImm' 2387590Sgblack@eecs.umich.edu nameFunc = staticmethod(storeImmClassName) 2397590Sgblack@eecs.umich.edu 2407590Sgblack@eecs.umich.edu def __init__(self, *args, **kargs): 2417590Sgblack@eecs.umich.edu super(StoreImmEx, self).__init__(*args, **kargs) 24212219Snikos.nikoleris@arm.com self.codeBlobs["postacc_code"] = \ 24312219Snikos.nikoleris@arm.com "Result = !writeResult; SevMailbox = 1; LLSCLock = 0;" 2447590Sgblack@eecs.umich.edu 2457590Sgblack@eecs.umich.edu class StoreImm(StoreImmInst, StoreSingle): 2467590Sgblack@eecs.umich.edu decConstBase = 'LoadStoreImm' 2477590Sgblack@eecs.umich.edu basePrefix = 'MemoryImm' 2487590Sgblack@eecs.umich.edu nameFunc = staticmethod(storeImmClassName) 2497590Sgblack@eecs.umich.edu 2507590Sgblack@eecs.umich.edu def storeRegClassName(post, add, writeback, size=4, sign=False, user=False): 2517590Sgblack@eecs.umich.edu return memClassName("STORE_REG", post, add, writeback, size, sign, user) 2527590Sgblack@eecs.umich.edu 2537590Sgblack@eecs.umich.edu class StoreReg(StoreRegInst, StoreSingle): 2547646Sgene.wu@arm.com decConstBase = 'StoreReg' 2557590Sgblack@eecs.umich.edu basePrefix = 'MemoryReg' 2567590Sgblack@eecs.umich.edu nameFunc = staticmethod(storeRegClassName) 2577590Sgblack@eecs.umich.edu 2587590Sgblack@eecs.umich.edu class StoreDouble(StoreInst): 2597590Sgblack@eecs.umich.edu def __init__(self, *args, **kargs): 2607590Sgblack@eecs.umich.edu super(StoreDouble, self).__init__(*args, **kargs) 2617590Sgblack@eecs.umich.edu 2627590Sgblack@eecs.umich.edu # Build the default class name 2637590Sgblack@eecs.umich.edu self.Name = self.nameFunc(self.post, self.add, self.writeback) 2647590Sgblack@eecs.umich.edu 2657590Sgblack@eecs.umich.edu # Add memory request flags where necessary 26613589Sgiacomo.travaglini@arm.com if self.flavor in ("exclusive", "relex"): 26713588Sgiacomo.travaglini@arm.com self.instFlags.append("IsStoreConditional") 2687590Sgblack@eecs.umich.edu self.memFlags.append("Request::LLSC") 2697593SAli.Saidi@arm.com self.memFlags.append("ArmISA::TLB::AlignDoubleWord") 2707593SAli.Saidi@arm.com else: 2717593SAli.Saidi@arm.com self.memFlags.append("ArmISA::TLB::AlignWord") 2727590Sgblack@eecs.umich.edu 27313589Sgiacomo.travaglini@arm.com if self.flavor in ("release", "relex"): 27413589Sgiacomo.travaglini@arm.com self.instFlags.extend(["IsMemBarrier", 27513589Sgiacomo.travaglini@arm.com "IsWriteBarrier", 27613589Sgiacomo.travaglini@arm.com "IsReadBarrier"]) 27713589Sgiacomo.travaglini@arm.com 2787590Sgblack@eecs.umich.edu # Disambiguate the class name for different flavors of stores 2797590Sgblack@eecs.umich.edu if self.flavor != "normal": 2807590Sgblack@eecs.umich.edu self.Name = "%s_%s" % (self.name.upper(), self.Name) 2817590Sgblack@eecs.umich.edu 2827590Sgblack@eecs.umich.edu def emit(self): 2837590Sgblack@eecs.umich.edu # Address computation code 2847590Sgblack@eecs.umich.edu eaCode = "EA = Base" 2857590Sgblack@eecs.umich.edu if not self.post: 2867590Sgblack@eecs.umich.edu eaCode += self.offset 2877590Sgblack@eecs.umich.edu eaCode += ";" 2887644Sali.saidi@arm.com 2897644Sali.saidi@arm.com if self.flavor == "fp": 2907644Sali.saidi@arm.com eaCode += vfpEnabledCheckCode 2917644Sali.saidi@arm.com 2927590Sgblack@eecs.umich.edu self.codeBlobs["ea_code"] = eaCode 2937590Sgblack@eecs.umich.edu 2947590Sgblack@eecs.umich.edu # Code that actually handles the access 2957590Sgblack@eecs.umich.edu if self.flavor == "fp": 2967590Sgblack@eecs.umich.edu accCode = ''' 2978588Sgblack@eecs.umich.edu uint64_t swappedMem = (uint64_t)FpDest_uw | 2988588Sgblack@eecs.umich.edu ((uint64_t)FpDest2_uw << 32); 2998588Sgblack@eecs.umich.edu Mem_ud = cSwap(swappedMem, ((CPSR)Cpsr).e); 3007590Sgblack@eecs.umich.edu ''' 3017590Sgblack@eecs.umich.edu else: 3027590Sgblack@eecs.umich.edu accCode = ''' 3037590Sgblack@eecs.umich.edu CPSR cpsr = Cpsr; 3048588Sgblack@eecs.umich.edu Mem_ud = (uint64_t)cSwap(Dest_uw, cpsr.e) | 3058588Sgblack@eecs.umich.edu ((uint64_t)cSwap(Dest2_uw, cpsr.e) << 32); 3067590Sgblack@eecs.umich.edu ''' 3077590Sgblack@eecs.umich.edu 3087590Sgblack@eecs.umich.edu self.codeBlobs["memacc_code"] = accCode 3097590Sgblack@eecs.umich.edu 3107590Sgblack@eecs.umich.edu # Push it out to the output files 3117590Sgblack@eecs.umich.edu base = buildMemBase(self.basePrefix, self.post, self.writeback) 3127646Sgene.wu@arm.com wbDecl = None 3137646Sgene.wu@arm.com if self.writeback: 3147646Sgene.wu@arm.com wbDecl = self.wbDecl 3157646Sgene.wu@arm.com self.emitHelper(base, wbDecl) 3167119SN/A 3177128Sgblack@eecs.umich.edu def storeDoubleImmClassName(post, add, writeback): 3187590Sgblack@eecs.umich.edu return memClassName("STORE_IMMD", post, add, writeback, 4, False, False) 3197590Sgblack@eecs.umich.edu 3207590Sgblack@eecs.umich.edu class StoreDoubleImmEx(StoreImmInst, StoreDouble): 3217590Sgblack@eecs.umich.edu execBase = 'StoreEx' 3227590Sgblack@eecs.umich.edu decConstBase = 'StoreExDImm' 3237590Sgblack@eecs.umich.edu basePrefix = 'MemoryExDImm' 3247590Sgblack@eecs.umich.edu nameFunc = staticmethod(storeDoubleImmClassName) 3257590Sgblack@eecs.umich.edu 3267590Sgblack@eecs.umich.edu def __init__(self, *args, **kargs): 3277590Sgblack@eecs.umich.edu super(StoreDoubleImmEx, self).__init__(*args, **kargs) 32812219Snikos.nikoleris@arm.com self.codeBlobs["postacc_code"] = \ 32912219Snikos.nikoleris@arm.com "Result = !writeResult; SevMailbox = 1; LLSCLock = 0;" 3307590Sgblack@eecs.umich.edu 3317590Sgblack@eecs.umich.edu class StoreDoubleImm(StoreImmInst, StoreDouble): 3327590Sgblack@eecs.umich.edu decConstBase = 'LoadStoreDImm' 3337590Sgblack@eecs.umich.edu basePrefix = 'MemoryDImm' 3347590Sgblack@eecs.umich.edu nameFunc = staticmethod(storeDoubleImmClassName) 3357128Sgblack@eecs.umich.edu 3367128Sgblack@eecs.umich.edu def storeDoubleRegClassName(post, add, writeback): 3377590Sgblack@eecs.umich.edu return memClassName("STORE_REGD", post, add, writeback, 4, False, False) 3387128Sgblack@eecs.umich.edu 3397590Sgblack@eecs.umich.edu class StoreDoubleReg(StoreRegInst, StoreDouble): 3407646Sgene.wu@arm.com decConstBase = 'StoreDReg' 3417590Sgblack@eecs.umich.edu basePrefix = 'MemoryDReg' 3427590Sgblack@eecs.umich.edu nameFunc = staticmethod(storeDoubleRegClassName) 3437128Sgblack@eecs.umich.edu 3447120Sgblack@eecs.umich.edu def buildStores(mnem, size=4, sign=False, user=False): 3457590Sgblack@eecs.umich.edu StoreImm(mnem, True, True, True, size, sign, user).emit() 3467590Sgblack@eecs.umich.edu StoreReg(mnem, True, True, True, size, sign, user).emit() 3477590Sgblack@eecs.umich.edu StoreImm(mnem, True, False, True, size, sign, user).emit() 3487590Sgblack@eecs.umich.edu StoreReg(mnem, True, False, True, size, sign, user).emit() 3497590Sgblack@eecs.umich.edu StoreImm(mnem, False, True, True, size, sign, user).emit() 3507590Sgblack@eecs.umich.edu StoreReg(mnem, False, True, True, size, sign, user).emit() 3517590Sgblack@eecs.umich.edu StoreImm(mnem, False, False, True, size, sign, user).emit() 3527590Sgblack@eecs.umich.edu StoreReg(mnem, False, False, True, size, sign, user).emit() 3537590Sgblack@eecs.umich.edu StoreImm(mnem, False, True, False, size, sign, user).emit() 3547590Sgblack@eecs.umich.edu StoreReg(mnem, False, True, False, size, sign, user).emit() 3557590Sgblack@eecs.umich.edu StoreImm(mnem, False, False, False, size, sign, user).emit() 3567590Sgblack@eecs.umich.edu StoreReg(mnem, False, False, False, size, sign, user).emit() 3577119SN/A 3587128Sgblack@eecs.umich.edu def buildDoubleStores(mnem): 3597590Sgblack@eecs.umich.edu StoreDoubleImm(mnem, True, True, True).emit() 3607590Sgblack@eecs.umich.edu StoreDoubleReg(mnem, True, True, True).emit() 3617590Sgblack@eecs.umich.edu StoreDoubleImm(mnem, True, False, True).emit() 3627590Sgblack@eecs.umich.edu StoreDoubleReg(mnem, True, False, True).emit() 3637590Sgblack@eecs.umich.edu StoreDoubleImm(mnem, False, True, True).emit() 3647590Sgblack@eecs.umich.edu StoreDoubleReg(mnem, False, True, True).emit() 3657590Sgblack@eecs.umich.edu StoreDoubleImm(mnem, False, False, True).emit() 3667590Sgblack@eecs.umich.edu StoreDoubleReg(mnem, False, False, True).emit() 3677590Sgblack@eecs.umich.edu StoreDoubleImm(mnem, False, True, False).emit() 3687590Sgblack@eecs.umich.edu StoreDoubleReg(mnem, False, True, False).emit() 3697590Sgblack@eecs.umich.edu StoreDoubleImm(mnem, False, False, False).emit() 3707590Sgblack@eecs.umich.edu StoreDoubleReg(mnem, False, False, False).emit() 3717128Sgblack@eecs.umich.edu 3727313Sgblack@eecs.umich.edu def buildSrsStores(mnem): 3737590Sgblack@eecs.umich.edu SrsInst(mnem, True, True, True).emit() 3747590Sgblack@eecs.umich.edu SrsInst(mnem, True, True, False).emit() 3757590Sgblack@eecs.umich.edu SrsInst(mnem, True, False, True).emit() 3767590Sgblack@eecs.umich.edu SrsInst(mnem, True, False, False).emit() 3777590Sgblack@eecs.umich.edu SrsInst(mnem, False, True, True).emit() 3787590Sgblack@eecs.umich.edu SrsInst(mnem, False, True, False).emit() 3797590Sgblack@eecs.umich.edu SrsInst(mnem, False, False, True).emit() 3807590Sgblack@eecs.umich.edu SrsInst(mnem, False, False, False).emit() 3817313Sgblack@eecs.umich.edu 3827120Sgblack@eecs.umich.edu buildStores("str") 3837120Sgblack@eecs.umich.edu buildStores("strt", user=True) 3847120Sgblack@eecs.umich.edu buildStores("strb", size=1) 3857120Sgblack@eecs.umich.edu buildStores("strbt", size=1, user=True) 3867120Sgblack@eecs.umich.edu buildStores("strh", size=2) 3877120Sgblack@eecs.umich.edu buildStores("strht", size=2, user=True) 3887128Sgblack@eecs.umich.edu 3897313Sgblack@eecs.umich.edu buildSrsStores("srs") 3907313Sgblack@eecs.umich.edu 3917128Sgblack@eecs.umich.edu buildDoubleStores("strd") 3927303Sgblack@eecs.umich.edu 39313588Sgiacomo.travaglini@arm.com StoreImmEx("strex", False, True, False, size=4, 39413588Sgiacomo.travaglini@arm.com flavor="exclusive").emit() 39513588Sgiacomo.travaglini@arm.com StoreImmEx("strexh", False, True, False, size=2, 39613588Sgiacomo.travaglini@arm.com flavor="exclusive").emit() 39713588Sgiacomo.travaglini@arm.com StoreImmEx("strexb", False, True, False, size=1, 39813588Sgiacomo.travaglini@arm.com flavor="exclusive").emit() 39913588Sgiacomo.travaglini@arm.com StoreDoubleImmEx("strexd", False, True, False, 40013588Sgiacomo.travaglini@arm.com flavor="exclusive").emit() 4017345Sgblack@eecs.umich.edu 40213589Sgiacomo.travaglini@arm.com StoreImm("stl", False, True, False, size=4, flavor="release").emit() 40313589Sgiacomo.travaglini@arm.com StoreImm("stlh", False, True, False, size=2, flavor="release").emit() 40413589Sgiacomo.travaglini@arm.com StoreImm("stlb", False, True, False, size=1, flavor="release").emit() 40513589Sgiacomo.travaglini@arm.com StoreImmEx("stlex", False, True, False, size=4, flavor="relex").emit() 40613589Sgiacomo.travaglini@arm.com StoreImmEx("stlexh", False, True, False, size=2, flavor="relex").emit() 40713589Sgiacomo.travaglini@arm.com StoreImmEx("stlexb", False, True, False, size=1, flavor="relex").emit() 40813589Sgiacomo.travaglini@arm.com StoreDoubleImmEx("stlexd", False, True, False, flavor="relex").emit() 40913589Sgiacomo.travaglini@arm.com 4107590Sgblack@eecs.umich.edu StoreImm("vstr", False, True, False, size=4, flavor="fp").emit() 4117590Sgblack@eecs.umich.edu StoreImm("vstr", False, False, False, size=4, flavor="fp").emit() 4127590Sgblack@eecs.umich.edu StoreDoubleImm("vstr", False, True, False, flavor="fp").emit() 4137590Sgblack@eecs.umich.edu StoreDoubleImm("vstr", False, False, False, flavor="fp").emit() 4147119SN/A}}; 415