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| H A D | faults.cc | 14279:0f25d914f4a8 Fri Sep 06 09:44:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: ISV bit in DataAbort should check for translation stage According to the ESR spec, the ISV bit is set to 1 only for stage 2 aborts. Change-Id: Id524ef36e82184f741e968ddba04ca8ccdd4ad58 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20980 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
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