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| H A D | smmu_v3_defs.hh | 14102:b0b52ccb7e1b Mon Jul 22 12:38:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> dev-arm: Define enum masks for SMMU_CR0 register The configuration register is a vital register in the SMMU, and using enum masks will make the code more readable/understandable Change-Id: Ia117db56c457fe876ae38be391c386e502f34384 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19632 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
| H A D | smmu_v3_transl.cc | 14102:b0b52ccb7e1b Mon Jul 22 12:38:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> dev-arm: Define enum masks for SMMU_CR0 register The configuration register is a vital register in the SMMU, and using enum masks will make the code more readable/understandable Change-Id: Ia117db56c457fe876ae38be391c386e502f34384 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19632 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
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