Searched hist:13895 (Results 1 - 4 of 4) sorted by relevance
/gem5/src/arch/arm/insts/ | ||
H A D | misc64.cc | 13895:5762b3dc79c6 Wed Feb 13 10:14:00 EST 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Report real instruction encoding when Undefined When dumping the opcode that caused an Undefined Instruction, we just want to dump the real instruction encoding, and not the extended version with metabits (like thumb, bigThumb etc). This was not appening when panicking in SE mode. The patch is also replacing custom masking in the Unknown(64) disassembler in favour of ArmStaticInstruction::encoding() helper. Change-Id: I9eb6fd145d02b4b07bb51f0bd89ca014d6d5a6de Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18395 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
H A D | misc.cc | 13895:5762b3dc79c6 Wed Feb 13 10:14:00 EST 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Report real instruction encoding when Undefined When dumping the opcode that caused an Undefined Instruction, we just want to dump the real instruction encoding, and not the extended version with metabits (like thumb, bigThumb etc). This was not appening when panicking in SE mode. The patch is also replacing custom masking in the Unknown(64) disassembler in favour of ArmStaticInstruction::encoding() helper. Change-Id: I9eb6fd145d02b4b07bb51f0bd89ca014d6d5a6de Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18395 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
/gem5/src/arch/arm/ | ||
H A D | faults.cc | 13895:5762b3dc79c6 Wed Feb 13 10:14:00 EST 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Report real instruction encoding when Undefined When dumping the opcode that caused an Undefined Instruction, we just want to dump the real instruction encoding, and not the extended version with metabits (like thumb, bigThumb etc). This was not appening when panicking in SE mode. The patch is also replacing custom masking in the Unknown(64) disassembler in favour of ArmStaticInstruction::encoding() helper. Change-Id: I9eb6fd145d02b4b07bb51f0bd89ca014d6d5a6de Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18395 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
/gem5/src/mem/cache/ | ||
H A D | base.cc | 13376:2165f3f012ed Fri Oct 26 10:40:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: Fix double block invalidation Block was being invalidated twice when not a tempBlock. Make explicit that the else case is only to be applied when handling the tempBlock, as otherwise the Tags should be taking care of the invalidation. Change-Id: Ie7603fdbe156c54e94bbdc83541b55e66f8d250f Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13895 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
Completed in 62 milliseconds